| /xsrc/external/mit/MesaLib/dist/src/gallium/auxiliary/gallivm/ |
| lp_bld_nir_soa.c | 2026 LLVMValueRef store_val = NULL; local
2034 store_val = LLVMBuildBitCast(builder, flt_max, int_bld->elem_type, "");
2040 store_val = LLVMBuildBitCast(builder, flt_min, int_bld->elem_type, "");
2046 store_val = LLVMBuildBitCast(builder, flt_one, int_bld->elem_type, "");
2052 store_val = LLVMConstInt(LLVMInt8TypeInContext(gallivm->context), UINT8_MAX, 0);
2055 store_val = LLVMConstInt(LLVMInt16TypeInContext(gallivm->context), UINT16_MAX, 0);
2059 store_val = lp_build_const_int32(gallivm, UINT_MAX);
2062 store_val = lp_build_const_int64(gallivm, UINT64_MAX);
2069 store_val = LLVMConstInt(LLVMInt8TypeInContext(gallivm->context), INT8_MAX, 0);
2072 store_val = LLVMConstInt(LLVMInt16TypeInContext(gallivm->context), INT16_MAX, 0)
2235 LLVMValueRef store_val = loop_state.counter; local
[all...] |
| /xsrc/external/mit/MesaLib/dist/src/amd/common/ |
| ac_nir_lower_esgs_io_to_mem.c | 101 nir_ssa_def *store_val = nir_extract_bits(b, &d, 1, start_byte * 8u, 1, store_bytes * 8u); local
102 nir_build_store_buffer_amd(b, store_val, desc, v_off, s_off, .is_swizzled = swizzled, .slc_amd = slc,
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| ac_nir_lower_ngg.c | 430 nir_ssa_def *store_val = intrin->src[0].ssa; local
431 nir_store_var(b, s->pre_cull_position_value_var, store_val, writemask);
514 nir_ssa_def *store_val = intrin->src[0].ssa; local
519 if (store_val->parent_instr->type == nir_instr_type_alu) {
520 nir_alu_instr *alu = nir_instr_as_alu(store_val->parent_instr);
545 rewrite_uses_to_var(b, store_val, s->pos_value_replacement, store_pos_component);
548 rewrite_uses_to_var(b, store_val, s->pos_value_replacement, store_pos_component);
833 nir_ssa_def *store_val = intrin->src[0].ssa; local
835 analyze_shader_before_culling_walk(store_val, flag, nogs_state);
1518 nir_ssa_def *store_val = intrin->src[0].ssa local
[all...] |
| ac_nir_lower_tess_io_to_mem.c | 395 nir_ssa_def *store_val = intrin->src[0].ssa; local
409 nir_build_store_buffer_amd(b, store_val, hs_ring_tess_offchip, vmem_off, offchip_offset, .write_mask = write_mask, .memory_modes = nir_var_shader_out);
420 nir_build_store_shared(b, store_val, lds_off, .write_mask = write_mask,
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| /xsrc/external/mit/MesaLib/dist/src/amd/compiler/ |
| aco_instruction_selection.cpp | 8919 Temp store_val = get_ssa_temp(ctx, instr->src[0].ssa);
8923 bld.ds(aco_opcode::ds_add_u32, as_vgpr(ctx, gds_addr), as_vgpr(ctx, store_val), m, 0u, 0u,
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