| /xsrc/external/mit/MesaLib/dist/src/compiler/nir/tests/ |
| H A D | builder_tests.cpp | 60 stores.push_back(store);
65 return stores[idx]->src[1].ssa;
68 std::vector<nir_intrinsic_instr *> stores; member in class:__anonec79332a0110::nir_builder_test
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| /xsrc/external/mit/MesaLib/dist/src/compiler/nir/ |
| H A D | nir_opt_combine_stores.c | 32 /* Combine stores of vectors to the same deref into a single store.
34 * This per-block pass keeps track of stores of vectors to the same
36 * stores (or parts of the store) found during the process are removed.
49 /* Keep track of a group of stores that can be combined. All stores share the
64 nir_intrinsic_instr *stores[NIR_MAX_VEC_COMPONENTS]; member in struct:combined_store
125 * gets build, remove previous stores that are not needed anymore.
131 nir_intrinsic_instr *store = combo->stores[i];
267 nir_intrinsic_instr *prev_store = combo->stores[i];
280 combo->stores[
[all...] |
| H A D | nir_lower_vars_to_ssa.c | 49 struct set *stores; member in struct:deref_node
84 * At the moment, we only lower loads, stores, and copies that can be
85 * trivially lowered to loads and stores, i.e. copies with no indirects
88 * wildcards, then we lower that copy operation to loads and stores, but
90 * used in these loads, stores, and trivial copies are ones with no
367 * direct load/stores.
429 if (node->stores == NULL)
430 node->stores = _mesa_pointer_set_create(state->dead_ctx);
432 _mesa_set_add(node->stores, store_instr);
783 if (node->stores) {
[all...] |
| H A D | nir_opt_load_store_vectorize.c | 26 * intersecting and identical loads/stores. It currently supports derefs, ubo,
27 * ssbo and push constant loads/stores.
59 int base_src; /* offset which it loads/stores from */
60 int deref_src; /* deref which is loads/stores from */
193 struct hash_table *stores[nir_num_variable_modes]; member in struct:vectorize_ctx
1109 /* we can only vectorize non-volatile loads/stores of the same type and with
1151 /* vectorize the loads/stores */
1257 /* prevent speculative loads/stores */
1308 assert(ctx->stores[mode_index] == NULL);
1315 *progress |= vectorize_entries(ctx, impl, ctx->stores[mode_inde
[all...] |
| /xsrc/external/mit/MesaLib.old/dist/src/compiler/nir/ |
| H A D | nir_opt_combine_stores.c | 32 /* Combine stores of vectors to the same deref into a single store.
34 * This per-block pass keeps track of stores of vectors to the same
36 * stores (or parts of the store) found during the process are removed.
49 /* Keep track of a group of stores that can be combined. All stores share the
64 nir_intrinsic_instr *stores[NIR_MAX_VEC_COMPONENTS]; member in struct:combined_store
125 * gets build, remove previous stores that are not needed anymore.
131 nir_intrinsic_instr *store = combo->stores[i];
267 nir_intrinsic_instr *prev_store = combo->stores[i];
280 combo->stores[
[all...] |
| H A D | nir_lower_vars_to_ssa.c | 49 struct set *stores; member in struct:deref_node
76 * At the moment, we only lower loads, stores, and copies that can be
77 * trivially lowered to loads and stores, i.e. copies with no indirects
80 * wildcards, then we lower that copy operation to loads and stores, but
82 * used in these loads, stores, and trivial copies are ones with no
350 * direct load/stores.
393 if (node->stores == NULL)
394 node->stores = _mesa_pointer_set_create(state->dead_ctx);
396 _mesa_set_add(node->stores, store_instr);
726 if (node->stores) {
[all...] |
| /xsrc/external/mit/MesaLib/dist/docs/relnotes/ |
| H A D | 19.2.7.rst | 67 - radv: set writes_memory for global memory stores/atomics
|
| H A D | 20.0.5.rst | 189 - ac/nir: split 8-bit SSBO stores on GFX6
192 - ac/nir: split 16-bit SSBO stores on GFX6
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| H A D | 18.3.4.rst | 55 - amd/common: Use correct writemask for shared memory stores.
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| H A D | 20.1.9.rst | 65 - intel/fs: Disable sample mask predication for scratch stores
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| H A D | 20.2.1.rst | 71 - intel/fs: Disable sample mask predication for scratch stores
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| H A D | 20.2.2.rst | 115 - nir/opt_load_store_vectorize: don't vectorize stores across demote
|
| H A D | 21.1.3.rst | 134 - aco: fix range checking for SSBO loads/stores with SGPR offset on GFX6-7
|
| H A D | 21.2.2.rst | 212 - radeonsi: disable DCC stores on Navi12-14 for displayable DCC to fix corruption
249 - radv: disable DCC image stores on Navi12-14 for displayable DCC corruption
|
| H A D | 20.3.5.rst | 248 - nir/opt_shrink_vectors: add option to skip shrinking image stores
249 - radv: don't shrink image stores for The Surge 2
|
| /xsrc/external/mit/MesaLib/dist/src/amd/compiler/ |
| H A D | README-ISA.md | 59 ## SMEM stores
62 the offset for SMEM stores must be in m0 if IMM == 0.
64 The RDNA ISA doesn't mention SMEM stores at all, but they seem to be supported
70 RDNA ISA: same as the SMEM stores, the ISA pretends they don't exist, but they
73 ## VMEM stores
208 SMEM stores, so it's not surprising that they didn't notice it.
|
| /xsrc/external/mit/MesaLib/dist/docs/ |
| H A D | dispatch.rst | 14 object, which is an implicit parameter to every GL function, stores all
49 Mesa uses two per-thread pointers. The first pointer stores the address
50 of the context current in the thread, and the second pointer stores the
52 dispatch table stores pointers to functions that actually implement
108 As long as an application is single threaded, Mesa stores a pointer to
243 To implement ``glXGetProcAddress``, Mesa stores a table that associates
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| /xsrc/external/mit/MesaLib/dist/src/amd/compiler/tests/ |
| H A D | README.md | 17 - A `$` in the pattern stores the output until the first whitespace character into a variable.
|
| H A D | test_hard_clause.cpp | 329 BEGIN_TEST(form_hard_clauses.stores)
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| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/r600/sfn/ |
| H A D | sfn_nir_lower_64bit.cpp | 205 unreachable("only splitting of stores to vars and arrays is supported");
964 void combine_one_slot(vector<nir_intrinsic_instr*>& stores);
1019 void StoreMerger::combine_one_slot(vector<nir_intrinsic_instr*>& stores) argument
1025 auto last_store = *stores.rbegin();
1032 for (auto&& store : stores) {
1050 for (auto i = stores.begin(); i != stores.end() - 1; ++i)
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| /xsrc/external/mit/fontconfig/dist/ |
| H A D | config.h.in | 267 /* Define to the sub-directory where libtool stores uninstalled libraries. */
412 /* Define WORDS_BIGENDIAN to 1 if your processor stores words with the most
|
| /xsrc/external/mit/xf86-video-intel/dist/ |
| H A D | config.h.in | 189 /* Define to the sub-directory where libtool stores uninstalled libraries. */
|
| /xsrc/external/mit/xf86-video-intel-2014/dist/ |
| H A D | config.h.in | 171 /* Define to the sub-directory in which libtool stores uninstalled libraries.
|
| /xsrc/external/mit/MesaLib/dist/docs/isl/ |
| H A D | aux-surf-comp.rst | 12 Broadwell and later. For this scheme, the auxiliary surface stores a single
|
| H A D | units.rst | 17 Each field in an ISL data structure that stores any sort of dimension has a
|