Searched refs:urb_gen5 (Results 1 - 6 of 6) sorted by relevance

/xsrc/external/mit/xf86-video-intel/dist/src/sna/brw/
H A Dbrw_eu_emit.c474 insn->bits3.urb_gen5.opcode = 1; /* FF_SYNC */
475 insn->bits3.urb_gen5.offset = 0; /* Not used by FF_SYNC */
476 insn->bits3.urb_gen5.swizzle_control = 0; /* Not used by FF_SYNC */
477 insn->bits3.urb_gen5.allocate = allocate;
478 insn->bits3.urb_gen5.used = 0; /* Not used by FF_SYNC */
479 insn->bits3.urb_gen5.complete = 0; /* Not used by FF_SYNC */
504 insn->bits3.urb_gen5.opcode = 0; /* URB_WRITE */
505 insn->bits3.urb_gen5.offset = offset;
506 insn->bits3.urb_gen5.swizzle_control = swizzle_control;
507 insn->bits3.urb_gen5
[all...]
H A Dbrw_disasm.c1020 format (file, " %d", inst->bits3.urb_gen5.offset);
1028 inst->bits3.urb_gen5.opcode, &space);
H A Dbrw_eu.h953 } urb_gen5; member in union:brw_instruction::__anon0c137b5d100a
/xsrc/external/mit/xf86-video-intel-2014/dist/src/sna/brw/
H A Dbrw_eu_emit.c474 insn->bits3.urb_gen5.opcode = 1; /* FF_SYNC */
475 insn->bits3.urb_gen5.offset = 0; /* Not used by FF_SYNC */
476 insn->bits3.urb_gen5.swizzle_control = 0; /* Not used by FF_SYNC */
477 insn->bits3.urb_gen5.allocate = allocate;
478 insn->bits3.urb_gen5.used = 0; /* Not used by FF_SYNC */
479 insn->bits3.urb_gen5.complete = 0; /* Not used by FF_SYNC */
504 insn->bits3.urb_gen5.opcode = 0; /* URB_WRITE */
505 insn->bits3.urb_gen5.offset = offset;
506 insn->bits3.urb_gen5.swizzle_control = swizzle_control;
507 insn->bits3.urb_gen5
[all...]
H A Dbrw_disasm.c1020 format (file, " %d", inst->bits3.urb_gen5.offset);
1028 inst->bits3.urb_gen5.opcode, &space);
H A Dbrw_eu.h953 } urb_gen5; member in union:brw_instruction::__anon2bd0c611100a

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