Searched refs:urb_gen7 (Results 1 - 4 of 4) sorted by relevance

/xsrc/external/mit/xf86-video-intel/dist/src/sna/brw/
H A Dbrw_eu_emit.c496 insn->bits3.urb_gen7.opcode = 0; /* URB_WRITE_HWORD */
497 insn->bits3.urb_gen7.offset = offset;
499 insn->bits3.urb_gen7.swizzle_control = swizzle_control;
501 insn->bits3.urb_gen7.per_slot_offset = 0;
502 insn->bits3.urb_gen7.complete = complete;
H A Dbrw_eu.h967 } urb_gen7; member in union:brw_instruction::__anon0c137b5d100a
/xsrc/external/mit/xf86-video-intel-2014/dist/src/sna/brw/
H A Dbrw_eu_emit.c496 insn->bits3.urb_gen7.opcode = 0; /* URB_WRITE_HWORD */
497 insn->bits3.urb_gen7.offset = offset;
499 insn->bits3.urb_gen7.swizzle_control = swizzle_control;
501 insn->bits3.urb_gen7.per_slot_offset = 0;
502 insn->bits3.urb_gen7.complete = complete;
H A Dbrw_eu.h967 } urb_gen7; member in union:brw_instruction::__anon2bd0c611100a

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