Searched refs:v1b (Results 1 - 9 of 9) sorted by relevance
| /xsrc/external/mit/MesaLib/dist/src/amd/compiler/tests/ |
| H A D | test_to_hw_instr.cpp | 150 Definition(v0_lo, v1b), Definition(v1_lo, v1b),
151 Operand(v1_lo, v1b), Operand(v0_lo, v1b));
154 //~gfx[67]! v1b: %0:v[1][24:32] = v_lshlrev_b32 24, %0:v[1][0:8]
160 Operand(v1_lo, v1b), Operand(v0_lo, v1b));
163 //~gfx[67]! v1b: %0:v[1][24:32] = v_lshlrev_b32 24, %0:v[1][0:8]
170 Definition(v0_lo, v3b), Operand(v1_lo, v1b),
171 Operand(v0_lo, v1b), Operan
[all...] |
| H A D | test_regalloc.cpp | 155 Temp tmp = bld.pseudo(aco_opcode::p_extract_vector, bld.def(v1b), inputs[0], Operand::zero());
173 Temp tmp = bld.pseudo(aco_opcode::p_extract_vector, bld.def(v1b), inputs[0], Operand::c32(4u));
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| H A D | test_sdwa.cpp | 40 sdwa = &bld.vop2_sdwa(aco_opcode::v_mul_f32, bld.def(v1b), inputs[0], inputs[1]).instr->sdwa();
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| /xsrc/external/mit/MesaLib/dist/docs/relnotes/ |
| H A D | 21.1.3.rst | 123 - aco: use v1b/v2b for ds_read_u8/ds_read_u16
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| H A D | 21.3.0.rst | 3582 - aco/ra: allow v1b operands with 16-bit instructions
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| H A D | 21.2.0.rst | 4451 - aco: use v1b/v2b for ds_read_u8/ds_read_u16
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| /xsrc/external/mit/MesaLib/dist/src/amd/compiler/ |
| H A D | aco_lower_to_hw_instr.cpp | 513 if (src.regClass() == v1b) {
1067 assert(dst.regClass() == v1b || dst.regClass() == v2b);
1069 if (dst.regClass() == v1b && ctx->program->chip_class >= GFX9) {
1267 tmp.op = Operand(op, v1b);
1268 tmp.def = Definition(def, v1b);
2143 assert(dst.regClass() == v2b || dst.regClass() == v1b || op.regClass() == v2b ||
2144 op.regClass() == v1b);
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| H A D | aco_ir.h | 326 v1b = v1 | (1 << 7), enumerator in enum:aco::RegClass::RC
393 static constexpr RegClass v1b{RegClass::v1b}; variable in namespace:aco
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| H A D | aco_instruction_selection.cpp | 1428 if (dst.regClass() == v1 || dst.regClass() == v2b || dst.regClass() == v1b) {
1557 } else if (dst.regClass() == v1 || dst.regClass() == v2b || dst.regClass() == v1b) {
1573 } else if (dst.regClass() == v1 || dst.regClass() == v2b || dst.regClass() == v1b) {
1589 } else if (dst.regClass() == v1 || dst.regClass() == v2b || dst.regClass() == v1b) {
2494 tmp = bld.pseudo(aco_opcode::p_extract_vector, bld.def(v1b), tmp, Operand::zero());
8291 if (src.regClass() == v1b || src.regClass() == v2b) {
8296 bld.def(src.regClass() == v1b ? v3b : v2b), tmp);
8343 if (src.regClass() == v1b || src.regClass() == v2b || src.regClass() == v1) {
8579 } else if (dst.regClass() == v1b) {
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