Searched refs:v2b (Results 1 - 10 of 10) sorted by relevance

/xsrc/external/mit/MesaLib/dist/src/amd/compiler/tests/
H A Dtest_to_hw_instr.cpp56 Definition(v0_lo, v2b), Definition(v1_lo, v2b),
57 Operand(v1_lo, v2b), Operand(v0_lo, v2b));
60 //~gfx[67]! v2b: %0:v[0][16:32] = v_lshlrev_b32 16, %0:v[0][0:16]
66 Operand(v1_lo, v2b), Operand(v0_lo, v2b));
69 //~gfx[67]! v2b: %0:v[0][16:32] = v_lshlrev_b32 16, %0:v[0][0:16]
72 //~gfx[67]! v2b: %0:v[1][0:16] = v_mov_b32 %0:v[2][0:16]
75 Definition(v0_lo, v6b), Operand(v1_lo, v2b),
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H A Dtest_regalloc.cpp46 //! v2b: %_:v[#a][0:16], v2b: %res1:v[#a][16:32] = p_split_vector %_:v[#a]
47 Builder::Result tmp = bld.pseudo(aco_opcode::p_split_vector, bld.def(v2b), bld.def(v2b), inputs[0]);
68 //! v2b: %_:v[0][0:16], v2b: %_:v[0][16:32] = p_split_vector %_:v[0]
69 Temp hi = bld.pseudo(aco_opcode::p_split_vector, bld.def(v2b), bld.def(v2b), inputs[0]).def(1).getTemp();
72 //! v2b: %_:v[0][0:16] = v_not_b32 0 dst_sel:uword0 dst_preserve src0_sel:dword
73 Temp lo = bld.vop1(aco_opcode::v_not_b32, bld.def(v2b), Operan
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H A Dtest_optimizer.cpp127 //! v2b: %res5 = v_add_f16 %a, %b *0.5
129 tmp = bld.vop2(aco_opcode::v_add_f16, bld.def(v2b), inputs[0], inputs[1]);
130 writeout(5, bld.vop2(aco_opcode::v_mul_f16, bld.def(v2b), Operand::c16(0x3800u), tmp));
132 //! v2b: %res6 = v_add_f16 %a, %b *2
134 tmp = bld.vop2(aco_opcode::v_add_f16, bld.def(v2b), inputs[0], inputs[1]);
135 writeout(6, bld.vop2(aco_opcode::v_mul_f16, bld.def(v2b), Operand::c16(0x4000u), tmp));
137 //! v2b: %res7 = v_add_f16 %a, %b *4
139 tmp = bld.vop2(aco_opcode::v_add_f16, bld.def(v2b), inputs[0], inputs[1]);
140 writeout(7, bld.vop2(aco_opcode::v_mul_f16, bld.def(v2b), Operand::c16(0x4400u), tmp));
142 //! v2b
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/xsrc/external/mit/MesaLib/dist/src/amd/compiler/
H A Daco_lower_to_hw_instr.cpp534 } else if (src.regClass() == v2b) {
1067 assert(dst.regClass() == v1b || dst.regClass() == v2b);
1081 } else if (dst.regClass() == v2b && ctx->program->chip_class >= GFX9 && !op.isLiteral()) {
1090 } else if (dst.regClass() == v2b && ctx->program->chip_class >= GFX10 &&
1093 Operand def_lo(dst.physReg().advance(-2), v2b);
1098 Operand def_hi(dst.physReg().advance(2), v2b);
1214 bld.vop2(aco_opcode::v_cvt_pk_u16_u32, dst, Operand(lo_reg, v2b), op);
1373 Definition def_lo = Definition(def.physReg(), v2b);
1374 Definition def_hi = Definition(def.physReg().advance(2), v2b);
1412 bld.vop1(aco_opcode::v_mov_b32, Definition(reg, v2b), o
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H A Daco_instruction_selection.cpp749 /* returns v2b or v1 for vop3p usage.
770 return emit_extract_vector(ctx, tmp, dword * 2, v2b);
1428 if (dst.regClass() == v1 || dst.regClass() == v2b || dst.regClass() == v1b) {
1491 if (dst.regClass() == v2b && ctx->program->chip_class >= GFX10) {
1493 } else if (dst.regClass() == v2b) {
1507 if (dst.regClass() == v2b && ctx->program->chip_class >= GFX10) {
1509 } else if (dst.regClass() == v2b) {
1523 if (dst.regClass() == v2b && ctx->program->chip_class >= GFX10) {
1525 } else if (dst.regClass() == v2b) {
1539 if (dst.regClass() == v2b
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H A Daco_ir.h327 v2b = v2 | (1 << 7), enumerator in enum:aco::RegClass::RC
394 static constexpr RegClass v2b{RegClass::v2b}; variable in namespace:aco
/xsrc/external/mit/MesaLib/dist/docs/relnotes/
H A D21.1.3.rst123 - aco: use v1b/v2b for ds_read_u8/ds_read_u16
H A D20.2.0.rst4267 - aco: remove unecessary p_split_vector with v2b reg class
4304 - aco: store 16-bit temporary outputs as v2b
H A D21.2.0.rst4451 - aco: use v1b/v2b for ds_read_u8/ds_read_u16
/xsrc/external/mit/MesaLib/dist/
H A D.pick_status.json18319 "description": "aco: use p_create_vector(v2b,v2b) in get_alu_src_vop3p()",
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