| /xsrc/external/mit/xf86-video-r128/dist/src/ |
| r128_crtc.c | 662 XclkFreq = pll->xclk;
739 XclkFreq = pll->xclk;
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| r128.h | 259 uint16_t xclk; member in struct:__anon168
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| r128_driver.c | 608 those to calculate xclk and find the reference divider */
629 pll->xclk = R128Div((2 * Nx * pll->reference_freq),
645 pll->xclk = 10300;
657 pll->xclk = R128_BIOS16(pll_info_block + 0x08);
662 "PLL parameters: rf=%d rd=%d min=%d max=%d; xclk=%d\n",
667 pll->xclk);
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| /xsrc/external/mit/xf86-video-ati/dist/src/ |
| radeon_mm_i2c.c | 451 nm=(pll->xclk * 40000.0)/(1.0*I2C_CLOCK_FREQ);
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| radeon_driver.c | 1014 unsigned xclk, tmp, ref_div; local
1157 /* Calculate "base" xclk straight from MPLL, though that isn't
1158 * really useful (hopefully). This isn't called XCLK anymore on
1164 xclk = RADEONDiv((2 * mpll_fb_div * xtal), (M));
1203 pll->xclk = xclk;
1262 pll->xclk = 10300;
1288 "PLL parameters: rf=%u rd=%u min=%u max=%u; xclk=%u\n",
1292 pll->xclk);
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| radeon_bios.c | 1014 pll->xclk = RADEON_BIOS16(pll_info_block + 0x08);
1025 "max_out_pll: %u, min_in_pll: %u, max_in_pll: %u, xclk: %d, "
1029 (unsigned)pll->pll_in_max, pll->xclk, info->sclk, info->mclk);
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| radeon.h | 298 uint16_t xclk; member in struct:__anon6803
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| radeon_atombios.c | 2282 pll->xclk = le16_to_cpu(atomDataPtr->FirmwareInfo.FirmwareInfo->usMaxPixelClock);
2295 pll->xclk = le16_to_cpu(atomDataPtr->FirmwareInfo.FirmwareInfo_V_1_2->usMaxPixelClock);
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| radeon_video.c | 1411 t->video_decoder_type, pll->xclk);
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