| /src/external/gpl3/binutils/dist/opcodes/ |
| s390-opc.c | 155 #define B_16 (C_12 + 1) /* Base register starting at position 16 */
157 #define B_32 (B_16 + 1) /* Base register starting at position 32 */
338 #define INSTR_RIS_RURDI 6, { R_8,I8_32,U4_12,D_20,B_16,0 } /* e.g. cib */
339 #define INSTR_RIS_R0RDI 6, { R_8,I8_32,D_20,B_16,0,0 } /* e.g. cibne */
340 #define INSTR_RIS_RURDU 6, { R_8,U8_32,U4_12,D_20,B_16,0 } /* e.g. clib */
341 #define INSTR_RIS_R0RDU 6, { R_8,U8_32,D_20,B_16,0,0 } /* e.g. clibne*/
410 #define INSTR_RRS_RRRDU 6, { R_8,R_12,U4_32,D_20,B_16 } /* e.g. crb */
411 #define INSTR_RRS_RRRD0 6, { R_8,R_12,D_20,B_16,0 } /* e.g. crbne */
412 #define INSTR_RSE_RRRD 6, { R_8,R_12,D_20,B_16,0,0 } /* e.g. lmh */
413 #define INSTR_RSE_RERERD 6, { RE_8,RE_12,D_20,B_16,0,0 } /* e.g. mvclu *
[all...] |
| s390-opc.c | 155 #define B_16 (C_12 + 1) /* Base register starting at position 16 */
157 #define B_32 (B_16 + 1) /* Base register starting at position 32 */
338 #define INSTR_RIS_RURDI 6, { R_8,I8_32,U4_12,D_20,B_16,0 } /* e.g. cib */
339 #define INSTR_RIS_R0RDI 6, { R_8,I8_32,D_20,B_16,0,0 } /* e.g. cibne */
340 #define INSTR_RIS_RURDU 6, { R_8,U8_32,U4_12,D_20,B_16,0 } /* e.g. clib */
341 #define INSTR_RIS_R0RDU 6, { R_8,U8_32,D_20,B_16,0,0 } /* e.g. clibne*/
410 #define INSTR_RRS_RRRDU 6, { R_8,R_12,U4_32,D_20,B_16 } /* e.g. crb */
411 #define INSTR_RRS_RRRD0 6, { R_8,R_12,D_20,B_16,0 } /* e.g. crbne */
412 #define INSTR_RSE_RRRD 6, { R_8,R_12,D_20,B_16,0,0 } /* e.g. lmh */
413 #define INSTR_RSE_RERERD 6, { RE_8,RE_12,D_20,B_16,0,0 } /* e.g. mvclu *
[all...] |
| s390-opc.c | 155 #define B_16 (C_12 + 1) /* Base register starting at position 16 */
157 #define B_32 (B_16 + 1) /* Base register starting at position 32 */
338 #define INSTR_RIS_RURDI 6, { R_8,I8_32,U4_12,D_20,B_16,0 } /* e.g. cib */
339 #define INSTR_RIS_R0RDI 6, { R_8,I8_32,D_20,B_16,0,0 } /* e.g. cibne */
340 #define INSTR_RIS_RURDU 6, { R_8,U8_32,U4_12,D_20,B_16,0 } /* e.g. clib */
341 #define INSTR_RIS_R0RDU 6, { R_8,U8_32,D_20,B_16,0,0 } /* e.g. clibne*/
410 #define INSTR_RRS_RRRDU 6, { R_8,R_12,U4_32,D_20,B_16 } /* e.g. crb */
411 #define INSTR_RRS_RRRD0 6, { R_8,R_12,D_20,B_16,0 } /* e.g. crbne */
412 #define INSTR_RSE_RRRD 6, { R_8,R_12,D_20,B_16,0,0 } /* e.g. lmh */
413 #define INSTR_RSE_RERERD 6, { RE_8,RE_12,D_20,B_16,0,0 } /* e.g. mvclu *
[all...] |
| /src/external/gpl3/binutils.old/dist/opcodes/ |
| s390-opc.c | 155 #define B_16 (C_12 + 1) /* Base register starting at position 16 */
157 #define B_32 (B_16 + 1) /* Base register starting at position 32 */
338 #define INSTR_RIS_RURDI 6, { R_8,I8_32,U4_12,D_20,B_16,0 } /* e.g. cib */
339 #define INSTR_RIS_R0RDI 6, { R_8,I8_32,D_20,B_16,0,0 } /* e.g. cibne */
340 #define INSTR_RIS_RURDU 6, { R_8,U8_32,U4_12,D_20,B_16,0 } /* e.g. clib */
341 #define INSTR_RIS_R0RDU 6, { R_8,U8_32,D_20,B_16,0,0 } /* e.g. clibne*/
410 #define INSTR_RRS_RRRDU 6, { R_8,R_12,U4_32,D_20,B_16 } /* e.g. crb */
411 #define INSTR_RRS_RRRD0 6, { R_8,R_12,D_20,B_16,0 } /* e.g. crbne */
412 #define INSTR_RSE_RRRD 6, { R_8,R_12,D_20,B_16,0,0 } /* e.g. lmh */
413 #define INSTR_RSE_RERERD 6, { RE_8,RE_12,D_20,B_16,0,0 } /* e.g. mvclu *
[all...] |
| s390-opc.c | 155 #define B_16 (C_12 + 1) /* Base register starting at position 16 */
157 #define B_32 (B_16 + 1) /* Base register starting at position 32 */
338 #define INSTR_RIS_RURDI 6, { R_8,I8_32,U4_12,D_20,B_16,0 } /* e.g. cib */
339 #define INSTR_RIS_R0RDI 6, { R_8,I8_32,D_20,B_16,0,0 } /* e.g. cibne */
340 #define INSTR_RIS_RURDU 6, { R_8,U8_32,U4_12,D_20,B_16,0 } /* e.g. clib */
341 #define INSTR_RIS_R0RDU 6, { R_8,U8_32,D_20,B_16,0,0 } /* e.g. clibne*/
410 #define INSTR_RRS_RRRDU 6, { R_8,R_12,U4_32,D_20,B_16 } /* e.g. crb */
411 #define INSTR_RRS_RRRD0 6, { R_8,R_12,D_20,B_16,0 } /* e.g. crbne */
412 #define INSTR_RSE_RRRD 6, { R_8,R_12,D_20,B_16,0,0 } /* e.g. lmh */
413 #define INSTR_RSE_RERERD 6, { RE_8,RE_12,D_20,B_16,0,0 } /* e.g. mvclu *
[all...] |
| s390-opc.c | 155 #define B_16 (C_12 + 1) /* Base register starting at position 16 */
157 #define B_32 (B_16 + 1) /* Base register starting at position 32 */
338 #define INSTR_RIS_RURDI 6, { R_8,I8_32,U4_12,D_20,B_16,0 } /* e.g. cib */
339 #define INSTR_RIS_R0RDI 6, { R_8,I8_32,D_20,B_16,0,0 } /* e.g. cibne */
340 #define INSTR_RIS_RURDU 6, { R_8,U8_32,U4_12,D_20,B_16,0 } /* e.g. clib */
341 #define INSTR_RIS_R0RDU 6, { R_8,U8_32,D_20,B_16,0,0 } /* e.g. clibne*/
410 #define INSTR_RRS_RRRDU 6, { R_8,R_12,U4_32,D_20,B_16 } /* e.g. crb */
411 #define INSTR_RRS_RRRD0 6, { R_8,R_12,D_20,B_16,0 } /* e.g. crbne */
412 #define INSTR_RSE_RRRD 6, { R_8,R_12,D_20,B_16,0,0 } /* e.g. lmh */
413 #define INSTR_RSE_RERERD 6, { RE_8,RE_12,D_20,B_16,0,0 } /* e.g. mvclu *
[all...] |
| /src/external/gpl3/gdb.old/dist/opcodes/ |
| s390-opc.c | 155 #define B_16 (C_12 + 1) /* Base register starting at position 16 */
157 #define B_32 (B_16 + 1) /* Base register starting at position 32 */
338 #define INSTR_RIS_RURDI 6, { R_8,I8_32,U4_12,D_20,B_16,0 } /* e.g. cib */
339 #define INSTR_RIS_R0RDI 6, { R_8,I8_32,D_20,B_16,0,0 } /* e.g. cibne */
340 #define INSTR_RIS_RURDU 6, { R_8,U8_32,U4_12,D_20,B_16,0 } /* e.g. clib */
341 #define INSTR_RIS_R0RDU 6, { R_8,U8_32,D_20,B_16,0,0 } /* e.g. clibne*/
410 #define INSTR_RRS_RRRDU 6, { R_8,R_12,U4_32,D_20,B_16 } /* e.g. crb */
411 #define INSTR_RRS_RRRD0 6, { R_8,R_12,D_20,B_16,0 } /* e.g. crbne */
412 #define INSTR_RSE_RRRD 6, { R_8,R_12,D_20,B_16,0,0 } /* e.g. lmh */
413 #define INSTR_RSE_RERERD 6, { RE_8,RE_12,D_20,B_16,0,0 } /* e.g. mvclu *
[all...] |
| s390-opc.c | 155 #define B_16 (C_12 + 1) /* Base register starting at position 16 */
157 #define B_32 (B_16 + 1) /* Base register starting at position 32 */
338 #define INSTR_RIS_RURDI 6, { R_8,I8_32,U4_12,D_20,B_16,0 } /* e.g. cib */
339 #define INSTR_RIS_R0RDI 6, { R_8,I8_32,D_20,B_16,0,0 } /* e.g. cibne */
340 #define INSTR_RIS_RURDU 6, { R_8,U8_32,U4_12,D_20,B_16,0 } /* e.g. clib */
341 #define INSTR_RIS_R0RDU 6, { R_8,U8_32,D_20,B_16,0,0 } /* e.g. clibne*/
410 #define INSTR_RRS_RRRDU 6, { R_8,R_12,U4_32,D_20,B_16 } /* e.g. crb */
411 #define INSTR_RRS_RRRD0 6, { R_8,R_12,D_20,B_16,0 } /* e.g. crbne */
412 #define INSTR_RSE_RRRD 6, { R_8,R_12,D_20,B_16,0,0 } /* e.g. lmh */
413 #define INSTR_RSE_RERERD 6, { RE_8,RE_12,D_20,B_16,0,0 } /* e.g. mvclu *
[all...] |
| s390-opc.c | 155 #define B_16 (C_12 + 1) /* Base register starting at position 16 */
157 #define B_32 (B_16 + 1) /* Base register starting at position 32 */
338 #define INSTR_RIS_RURDI 6, { R_8,I8_32,U4_12,D_20,B_16,0 } /* e.g. cib */
339 #define INSTR_RIS_R0RDI 6, { R_8,I8_32,D_20,B_16,0,0 } /* e.g. cibne */
340 #define INSTR_RIS_RURDU 6, { R_8,U8_32,U4_12,D_20,B_16,0 } /* e.g. clib */
341 #define INSTR_RIS_R0RDU 6, { R_8,U8_32,D_20,B_16,0,0 } /* e.g. clibne*/
410 #define INSTR_RRS_RRRDU 6, { R_8,R_12,U4_32,D_20,B_16 } /* e.g. crb */
411 #define INSTR_RRS_RRRD0 6, { R_8,R_12,D_20,B_16,0 } /* e.g. crbne */
412 #define INSTR_RSE_RRRD 6, { R_8,R_12,D_20,B_16,0,0 } /* e.g. lmh */
413 #define INSTR_RSE_RERERD 6, { RE_8,RE_12,D_20,B_16,0,0 } /* e.g. mvclu *
[all...] |
| /src/external/gpl3/gdb/dist/opcodes/ |
| s390-opc.c | 155 #define B_16 (C_12 + 1) /* Base register starting at position 16 */
157 #define B_32 (B_16 + 1) /* Base register starting at position 32 */
338 #define INSTR_RIS_RURDI 6, { R_8,I8_32,U4_12,D_20,B_16,0 } /* e.g. cib */
339 #define INSTR_RIS_R0RDI 6, { R_8,I8_32,D_20,B_16,0,0 } /* e.g. cibne */
340 #define INSTR_RIS_RURDU 6, { R_8,U8_32,U4_12,D_20,B_16,0 } /* e.g. clib */
341 #define INSTR_RIS_R0RDU 6, { R_8,U8_32,D_20,B_16,0,0 } /* e.g. clibne*/
410 #define INSTR_RRS_RRRDU 6, { R_8,R_12,U4_32,D_20,B_16 } /* e.g. crb */
411 #define INSTR_RRS_RRRD0 6, { R_8,R_12,D_20,B_16,0 } /* e.g. crbne */
412 #define INSTR_RSE_RRRD 6, { R_8,R_12,D_20,B_16,0,0 } /* e.g. lmh */
413 #define INSTR_RSE_RERERD 6, { RE_8,RE_12,D_20,B_16,0,0 } /* e.g. mvclu *
[all...] |
| s390-opc.c | 155 #define B_16 (C_12 + 1) /* Base register starting at position 16 */
157 #define B_32 (B_16 + 1) /* Base register starting at position 32 */
338 #define INSTR_RIS_RURDI 6, { R_8,I8_32,U4_12,D_20,B_16,0 } /* e.g. cib */
339 #define INSTR_RIS_R0RDI 6, { R_8,I8_32,D_20,B_16,0,0 } /* e.g. cibne */
340 #define INSTR_RIS_RURDU 6, { R_8,U8_32,U4_12,D_20,B_16,0 } /* e.g. clib */
341 #define INSTR_RIS_R0RDU 6, { R_8,U8_32,D_20,B_16,0,0 } /* e.g. clibne*/
410 #define INSTR_RRS_RRRDU 6, { R_8,R_12,U4_32,D_20,B_16 } /* e.g. crb */
411 #define INSTR_RRS_RRRD0 6, { R_8,R_12,D_20,B_16,0 } /* e.g. crbne */
412 #define INSTR_RSE_RRRD 6, { R_8,R_12,D_20,B_16,0,0 } /* e.g. lmh */
413 #define INSTR_RSE_RERERD 6, { RE_8,RE_12,D_20,B_16,0,0 } /* e.g. mvclu *
[all...] |
| s390-opc.c | 155 #define B_16 (C_12 + 1) /* Base register starting at position 16 */
157 #define B_32 (B_16 + 1) /* Base register starting at position 32 */
338 #define INSTR_RIS_RURDI 6, { R_8,I8_32,U4_12,D_20,B_16,0 } /* e.g. cib */
339 #define INSTR_RIS_R0RDI 6, { R_8,I8_32,D_20,B_16,0,0 } /* e.g. cibne */
340 #define INSTR_RIS_RURDU 6, { R_8,U8_32,U4_12,D_20,B_16,0 } /* e.g. clib */
341 #define INSTR_RIS_R0RDU 6, { R_8,U8_32,D_20,B_16,0,0 } /* e.g. clibne*/
410 #define INSTR_RRS_RRRDU 6, { R_8,R_12,U4_32,D_20,B_16 } /* e.g. crb */
411 #define INSTR_RRS_RRRD0 6, { R_8,R_12,D_20,B_16,0 } /* e.g. crbne */
412 #define INSTR_RSE_RRRD 6, { R_8,R_12,D_20,B_16,0,0 } /* e.g. lmh */
413 #define INSTR_RSE_RERERD 6, { RE_8,RE_12,D_20,B_16,0,0 } /* e.g. mvclu *
[all...] |
