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    Searched defs:Instr (Results 1 - 25 of 33) sorted by relevancy

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  /src/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/
NVPTXImageOptimizer.cpp 64 Instruction &Instr = *I;
72 Changed |= replaceIsTypePSampler(Instr);
75 Changed |= replaceIsTypePSurface(Instr);
78 Changed |= replaceIsTypePTexture(Instr);
  /src/external/apache2/llvm/dist/llvm/tools/llvm-exegesis/lib/
SerialSnippetGenerator.cpp 38 computeAliasingInstructions(const LLVMState &State, const Instruction *Instr,
49 if (OtherOpcode == Instr->Description.getOpcode())
63 if (Instr->hasAliasingRegistersThrough(OtherInstr, ForbiddenRegisters))
71 static ExecutionMode getExecutionModes(const Instruction &Instr,
74 if (Instr.hasAliasingImplicitRegisters())
76 if (Instr.hasTiedRegisters())
78 if (Instr.hasMemoryOperands())
81 if (Instr.hasAliasingRegisters(ForbiddenRegisters))
83 if (Instr.hasOneUseOrOneDef())
121 "Instr must alias itself explicitly")
    [all...]
CodeTemplate.h 26 InstructionTemplate(const Instruction *Instr);
39 const Instruction &getInstr() const { return *Instr; }
53 const Instruction *Instr;
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
DbgEntityHistoryCalculator.h 79 Entry(const MachineInstr *Instr, EntryKind Kind)
80 : Instr(Instr, Kind), EndIndex(NoEntry) {}
82 const MachineInstr *getInstr() const { return Instr.getPointer(); }
84 EntryKind getEntryKind() const { return Instr.getInt(); }
93 PointerIntPair<const MachineInstr *, 1, EntryKind> Instr;
ScheduleDAG.h 247 MachineInstr *Instr = nullptr; ///< Alternatively, a MachineInstr.
319 SUnit(MachineInstr *instr, unsigned nodenum)
320 : Instr(instr), NodeNum(nodenum), isVRegCycle(false), isCall(false),
349 assert(!Instr && "Setting SDNode of SUnit with MachineInstr!");
356 assert(!Instr && "Reading SDNode of SUnit with MachineInstr!");
362 bool isInstr() const { return Instr; }
368 Instr = MI;
375 return Instr;
  /src/external/apache2/llvm/dist/llvm/utils/TableGen/GlobalISel/
GIMatchDagPredicate.h 80 const CodeGenInstruction &Instr;
84 const CodeGenInstruction &Instr);
90 const CodeGenInstruction *getInstr() const { return &Instr; }
105 void addOpcode(const CodeGenInstruction *Instr) { Instrs.push_back(Instr); }
GIMatchTree.cpp 109 void GIMatchTreeBuilderLeafInfo::declareInstr(const GIMatchDagInstr *Instr, unsigned ID) {
110 // Record the assignment of this instr to the given ID.
112 Instr, GIMatchTreeInstrInfo(ID, Instr)));
115 if (Instr == nullptr)
118 if (!Instr->getUserAssignedName().empty())
119 Info.bindInstrVariable(Instr->getUserAssignedName(), ID);
120 for (const auto &VarBinding : Instr->user_assigned_operand_names())
123 // Clear the bit indicating we haven't visited this instr.
124 const auto &NodeI = find(MatchDag.instr_nodes(), Instr);
    [all...]
  /src/external/apache2/llvm/dist/llvm/tools/llvm-exegesis/
llvm-exegesis.cpp 252 const Instruction &Instr = State.getIC().getInstr(Opcode);
253 const MCInstrDesc &InstrDesc = Instr.Description;
265 Instr, MaxConfigsPerOpcode);
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/
RegBankSelect.h 207 MachineInstr &Instr;
209 /// Does the insertion point is before or after Instr.
216 return Instr;
217 return Instr.getNextNode() ? *Instr.getNextNode()
218 : Instr.getParent()->end();
222 return *Instr.getParent();
226 /// Create an insertion point before (\p Before=true) or after \p Instr.
227 InstrInsertPoint(MachineInstr &Instr, bool Before = true);
  /src/external/apache2/llvm/dist/llvm/lib/Analysis/
StackLifetime.cpp 370 const Instruction *Instr = dyn_cast<Instruction>(&V);
371 if (!Instr || !SL.isReachable(Instr))
376 if (SL.isAliveAfter(KV.getFirst(), Instr))
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
R600OptimizeVectorRegisters.cpp 51 MachineInstr *Instr;
55 RegSeqInfo(MachineRegisterInfo &MRI, MachineInstr *MI) : Instr(MI) {
57 for (unsigned i = 1, e = Instr->getNumOperands(); i < e; i+=2) {
58 MachineOperand &MO = Instr->getOperand(i);
59 unsigned Chan = Instr->getOperand(i + 1).getImm();
70 return RSI.Instr == Instr;
185 Register Reg = RSI->Instr->getOperand(0).getReg();
186 MachineBasicBlock::iterator Pos = RSI->Instr;
190 Register SrcVec = BaseRSI->Instr->getOperand(0).getReg()
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/
LanaiInstrInfo.cpp 321 const MachineInstr &Instr = *I;
323 if (Instr.modifiesRegister(Lanai::SR, TRI) ||
324 Instr.readsRegister(Lanai::SR, TRI))
356 const MachineInstr &Instr = *I;
357 for (unsigned IO = 0, EO = Instr.getNumOperands(); !isSafe && IO != EO;
359 const MachineOperand &MO = Instr.getOperand(IO);
372 CC = (LPCC::CondCode)Instr.getOperand(IO - 1).getImm();
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/Vectorize/
LoopVectorizationPlanner.h 49 VPInstruction *Instr = new VPInstruction(Opcode, Operands);
51 BB->insert(Instr, InsertPt);
52 return Instr;
355 /// leading from the loop exit instr to the phi need to be converted to
VPlan.cpp 55 const VPInstruction *Instr = dyn_cast<VPInstruction>(&V);
57 (Instr && Instr->getParent()) ? Instr->getParent()->getPlan() : nullptr);
97 const VPRecipeBase *Instr = dyn_cast_or_null<VPRecipeBase>(this->Def);
99 (Instr && Instr->getParent()) ? Instr->getParent()->getPlan() : nullptr);
105 const VPRecipeBase *Instr = dyn_cast_or_null<VPRecipeBase>(this);
107 (Instr && Instr->getParent()) ? Instr->getParent()->getPlan() : nullptr)
    [all...]
  /src/external/apache2/llvm/dist/llvm/tools/llvm-cfi-verify/lib/
FileAnalysis.h 78 struct Instr {
82 bool Valid; // Is this a valid instruction? If false, Instr::Instruction is
98 const Instr *getInstruction(uint64_t Address) const;
102 const Instr &getInstructionOrDie(uint64_t Address) const;
107 const Instr *getPrevInstructionSequential(const Instr &InstrMeta) const;
108 const Instr *getNextInstructionSequential(const Instr &InstrMeta) const;
111 bool isCFITrap(const Instr &InstrMeta) const;
115 bool willTrapOnCFIViolation(const Instr &InstrMeta) const
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsBranchExpansion.cpp 216 Iter Instr = getNextMachineInstrInBB(Position);
217 if (Instr == Parent->end()) {
218 return getNextMachineInstr(Instr, Parent);
220 return std::make_pair(Instr, false);
395 MachineInstrBuilder Instr =
398 Instr.addImm(0);
MipsInstructionSelector.cpp 742 struct Instr {
745 Instr(unsigned Opcode, Register Def, Register LHS, Register RHS)
755 SmallVector<struct Instr, 2> Instructions;
805 for (const struct Instr &Instruction : Instructions) {
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/Utils/
Debugify.cpp 410 auto Instr = L.first;
414 auto WeakInstrPtr = InstToDelete.find(Instr);
418 auto FnName = Instr->getFunction()->getName();
419 auto BB = Instr->getParent();
421 auto InstName = Instruction::getOpcodeName(Instr->getOpcode());
423 auto InstrIt = DILocsBefore.find(Instr);
429 {"instr", InstName},
433 << " did not generate DILocation for " << *Instr
440 // If the instr had the !dbg attached before the pass, consider it as
446 {"instr", InstName}
    [all...]
  /src/external/apache2/llvm/dist/llvm/tools/llvm-exegesis/lib/X86/
Target.cpp 58 static const char *isInvalidMemoryInstr(const Instruction &Instr) {
59 switch (Instr.Description.TSFlags & X86II::FormMask) {
158 return (Instr.Description.Opcode == X86::POP16r ||
159 Instr.Description.Opcode == X86::POP32r ||
160 Instr.Description.Opcode == X86::PUSH16r ||
161 Instr.Description.Opcode == X86::PUSH32r)
193 static const char *isInvalidOpcode(const Instruction &Instr) {
194 const auto OpcodeName = Instr.Name;
195 if ((Instr.Description.TSFlags & X86II::FormMask) == X86II::Pseudo)
201 switch (Instr.Description.Opcode)
    [all...]
  /src/external/apache2/llvm/dist/llvm/utils/TableGen/
CodeGenTarget.cpp 473 const CodeGenInstruction *Instr = GetInstByName(*p, Insts, Records);
474 assert(Instr && "Missing target independent instruction");
475 assert(Instr->Namespace == "TargetOpcode" && "Bad namespace");
476 InstrsByEnum.push_back(Instr);
491 assert(InstrsByEnum.size() == Insts.size() && "Missing predefined instr");
GICombinerEmitter.cpp 403 auto &Instr =
410 MatchDag.getContext().makeOperandList(Instr));
412 N->setOpcodeAnnotation(&Instr);
414 makeNameForAnonPredicate(*this), Instr);
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
MVETPAndVPTOptimisationsPass.cpp 71 MachineInstr &Instr,
536 static ARMCC::CondCodes GetCondCode(MachineInstr &Instr) {
537 assert(IsVCMP(Instr.getOpcode()) && "Inst must be a VCMP");
538 return ARMCC::CondCodes(Instr.getOperand(3).getImm());
568 // Returns true if Instr writes to VCCR.
569 static bool IsWritingToVCCR(MachineInstr &Instr) {
570 if (Instr.getNumOperands() == 0)
572 MachineOperand &Dst = Instr.getOperand(0);
578 MachineRegisterInfo &RegInfo = Instr.getMF()->getRegInfo();
584 // <Instr that uses %A ('User' Operand)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCLoopInstrFormPrep.cpp 1 //===------ PPCLoopInstrFormPrep.cpp - Loop Instr Form Prep Pass ----------===//
44 #define DEBUG_TYPE "ppc-loop-instr-form-prep"
128 BucketElement(const SCEVConstant *O, Instruction *I) : Offset(O), Instr(I) {}
129 BucketElement(Instruction *I) : Offset(nullptr), Instr(I) {}
132 Instruction *Instr;
463 if (auto *II = dyn_cast<IntrinsicInst>(BucketChain.Elements[j].Instr))
507 Instruction *MemI = BucketChain.Elements.begin()->Instr;
630 Value *Ptr = GetPointerOperand(I->Instr);
646 PtrIP = I->Instr;
650 getInstrName(I->Instr, GEPNodeOffNameSuffix), PtrIP)
    [all...]
  /src/external/apache2/llvm/dist/llvm/include/llvm/IR/
DiagnosticInfo.h 138 const Instruction *Instr = nullptr;
157 /// \p Instr gives the original instruction that triggered the diagnostic.
167 const Instruction *getInstruction() const { return Instr; }
696 /// Instr.
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/Instrumentation/
InstrProfiling.cpp 438 static InstrProfIncrementInst *castToIncrementInst(Instruction *Instr) {
439 InstrProfIncrementInst *Inc = dyn_cast<InstrProfIncrementInstStep>(Instr);
442 return dyn_cast<InstrProfIncrementInst>(Instr);
450 auto Instr = I++;
451 InstrProfIncrementInst *Inc = castToIncrementInst(&*Instr);
455 } else if (auto *Ind = dyn_cast<InstrProfValueProfileInst>(Instr)) {

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