| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| LiveInterval.h | 94 const bool Kill;
98 bool Kill)
99 : EarlyVal(EarlyVal), LateVal(LateVal), EndPoint(EndPoint), Kill(Kill)
113 return Kill;
489 SlotIndex StartIdx, SlotIndex Kill);
496 VNInfo *extendInBlock(SlotIndex StartIdx, SlotIndex Kill);
546 bool Kill = false;
552 Kill = true;
554 return LiveQueryResult(EarlyVal, LateVal, EndPoint, Kill);
[all...] |
| LiveRangeCalc.h | 112 // determined, the range from the block start to Kill will be added to LI.
113 SlotIndex Kill;
118 LiveInBlock(LiveRange &LR, MachineDomTreeNode *node, SlotIndex kill)
119 : LR(LR), DomNode(node), Kill(kill) {}
134 /// Find the set of defs that can reach @p Kill. @p Kill must belong to
137 /// If exactly one def can reach @p UseMBB, and the def dominates @p Kill,
146 /// is non-empty and @p Kill is jointly dominated only by the entries of
241 /// @param Kill Index in block where LI is killed. If the value i
[all...] |
| LiveInterval.h | 94 const bool Kill;
98 bool Kill)
99 : EarlyVal(EarlyVal), LateVal(LateVal), EndPoint(EndPoint), Kill(Kill)
113 return Kill;
489 SlotIndex StartIdx, SlotIndex Kill);
496 VNInfo *extendInBlock(SlotIndex StartIdx, SlotIndex Kill);
546 bool Kill = false;
552 Kill = true;
554 return LiveQueryResult(EarlyVal, LateVal, EndPoint, Kill);
[all...] |
| LiveRangeCalc.h | 112 // determined, the range from the block start to Kill will be added to LI.
113 SlotIndex Kill;
118 LiveInBlock(LiveRange &LR, MachineDomTreeNode *node, SlotIndex kill)
119 : LR(LR), DomNode(node), Kill(kill) {}
134 /// Find the set of defs that can reach @p Kill. @p Kill must belong to
137 /// If exactly one def can reach @p UseMBB, and the def dominates @p Kill,
146 /// is non-empty and @p Kill is jointly dominated only by the entries of
241 /// @param Kill Index in block where LI is killed. If the value i
[all...] |
| MachineInstrBuilder.h | 48 Kill = 0x8,
64 ImplicitKill = Implicit | Kill
104 flags & RegState::Kill,
509 return B ? RegState::Kill : 0;
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| MachineInstrBuilder.h | 48 Kill = 0x8,
64 ImplicitKill = Implicit | Kill
104 flags & RegState::Kill,
509 return B ? RegState::Kill : 0;
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| SIPostRABundler.cpp | 177 // TODO: Should maybe back-propagate kill flags to the bundle.
184 MachineInstr &Kill = *Next;
185 collectUsedRegUnits(Kill, KillUsedRegUnits);
189 // Erase the kill if it's a subset of the used registers.
195 Kill.eraseFromParent();
|
| SIPostRABundler.cpp | 177 // TODO: Should maybe back-propagate kill flags to the bundle.
184 MachineInstr &Kill = *Next;
185 collectUsedRegUnits(Kill, KillUsedRegUnits);
189 // Erase the kill if it's a subset of the used registers.
195 Kill.eraseFromParent();
|
| SIFormMemoryClauses.cpp | 142 S |= RegState::Kill;
312 // Debug instructions should not change the kill insertion.
342 // Track the last inserted kill.
343 MachineInstrBuilder Kill;
345 // Insert one kill per register, with operands covering all necessary
358 KillOps.emplace_back(R.second.first | RegState::Kill,
377 KillOps.emplace_back(R.second.first | RegState::Kill, SubReg);
385 // already have existing uses beyond the bundle, we don't need the kill.
389 Kill = BuildMI(*MI.getParent(), std::next(LastClauseInst),
390 DebugLoc(), TII->get(AMDGPU::KILL));
[all...] |
| SIFormMemoryClauses.cpp | 142 S |= RegState::Kill;
312 // Debug instructions should not change the kill insertion.
342 // Track the last inserted kill.
343 MachineInstrBuilder Kill;
345 // Insert one kill per register, with operands covering all necessary
358 KillOps.emplace_back(R.second.first | RegState::Kill,
377 KillOps.emplace_back(R.second.first | RegState::Kill, SubReg);
385 // already have existing uses beyond the bundle, we don't need the kill.
389 Kill = BuildMI(*MI.getParent(), std::next(LastClauseInst),
390 DebugLoc(), TII->get(AMDGPU::KILL));
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64ExpandPseudoInsts.cpp | 226 .addReg(AArch64::NZCV, RegState::Implicit | RegState::Kill);
313 .addUse(StatusReg, RegState::Kill)
314 .addUse(StatusReg, RegState::Kill)
542 .addReg(MI.getOperand(DOPIdx).getReg(), RegState::Kill)
547 .addReg(MI.getOperand(DOPIdx).getReg(), RegState::Kill)
645 bool Kill = (Offset + 1 == N) ? MI.getOperand(1).isKill() : false;
652 .addReg(MI.getOperand(1).getReg(), getKillRegState(Kill))
825 RegState::Kill |
933 .addReg(DstReg, RegState::Kill)
939 .addUse(DstReg, RegState::Kill);
[all...] |
| AArch64ExpandPseudoInsts.cpp | 226 .addReg(AArch64::NZCV, RegState::Implicit | RegState::Kill);
313 .addUse(StatusReg, RegState::Kill)
314 .addUse(StatusReg, RegState::Kill)
542 .addReg(MI.getOperand(DOPIdx).getReg(), RegState::Kill)
547 .addReg(MI.getOperand(DOPIdx).getReg(), RegState::Kill)
645 bool Kill = (Offset + 1 == N) ? MI.getOperand(1).isKill() : false;
652 .addReg(MI.getOperand(1).getReg(), getKillRegState(Kill))
825 RegState::Kill |
933 .addReg(DstReg, RegState::Kill)
939 .addUse(DstReg, RegState::Kill);
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| RegAllocFast.cpp | 276 MCPhysReg AssignedReg, bool Kill, bool LiveOut);
405 MCPhysReg AssignedReg, bool Kill, bool LiveOut) {
412 TII->storeRegToStackSlot(*MBB, Before, AssignedReg, Kill, FI, &RC, TRI);
544 /// not used by a virtreg. Kill the physreg, marking it free. This may add
863 .addReg(LRI->PhysReg, llvm::RegState::Kill);
913 bool Kill = LRI->LastUse == nullptr;
914 spill(SpillBefore, VirtReg, PhysReg, Kill, LRI->LiveOut);
941 // It is a last (killing) use without the kill flag; add the flag now.
946 assert((!MO.isKill() || LRI->LastUse == &MI) && "Invalid kill flag");
996 // A kill flag implies killing the full register. Add corresponding supe
[all...] |
| RegAllocFast.cpp | 276 MCPhysReg AssignedReg, bool Kill, bool LiveOut);
405 MCPhysReg AssignedReg, bool Kill, bool LiveOut) {
412 TII->storeRegToStackSlot(*MBB, Before, AssignedReg, Kill, FI, &RC, TRI);
544 /// not used by a virtreg. Kill the physreg, marking it free. This may add
863 .addReg(LRI->PhysReg, llvm::RegState::Kill);
913 bool Kill = LRI->LastUse == nullptr;
914 spill(SpillBefore, VirtReg, PhysReg, Kill, LRI->LiveOut);
941 // It is a last (killing) use without the kill flag; add the flag now.
946 assert((!MO.isKill() || LRI->LastUse == &MI) && "Invalid kill flag");
996 // A kill flag implies killing the full register. Add corresponding supe
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonInstrInfo.cpp | 1059 unsigned Kill = getKillRegState(MI.getOperand(1).isKill());
1062 .addReg(SrcLo, Kill | UndefLo);
1110 .addReg(BaseOp.getReg(), getRegState(BaseOp) & ~RegState::Kill)
1148 .addReg(BaseOp.getReg(), getRegState(BaseOp) & ~RegState::Kill)
1289 unsigned S = Op0.getReg() != Op3.getReg() ? PState & ~RegState::Kill
1322 unsigned S = Op0.getReg() != Op3.getReg() ? PState & ~RegState::Kill
|
| HexagonInstrInfo.cpp | 1059 unsigned Kill = getKillRegState(MI.getOperand(1).isKill());
1062 .addReg(SrcLo, Kill | UndefLo);
1110 .addReg(BaseOp.getReg(), getRegState(BaseOp) & ~RegState::Kill)
1148 .addReg(BaseOp.getReg(), getRegState(BaseOp) & ~RegState::Kill)
1289 unsigned S = Op0.getReg() != Op3.getReg() ? PState & ~RegState::Kill
1322 unsigned S = Op0.getReg() != Op3.getReg() ? PState & ~RegState::Kill
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