| /src/external/apache2/llvm/dist/llvm/lib/Transforms/InstCombine/ |
| InstCombineAtomicRMW.cpp | 22 /// ordering effects on nearby instructions, or be volatile.
114 AtomicOrdering Ordering = RMWI.getOrdering();
115 assert(Ordering != AtomicOrdering::NotAtomic &&
116 Ordering != AtomicOrdering::Unordered &&
120 // ordering is compatible.
123 if (Ordering != AtomicOrdering::Release &&
124 Ordering != AtomicOrdering::Monotonic)
128 SI->setAtomic(Ordering, RMWI.getSyncScopeID());
150 // Check if the required ordering is compatible with an atomic load.
151 if (Ordering != AtomicOrdering::Acquire &
[all...] |
| InstCombineAtomicRMW.cpp | 22 /// ordering effects on nearby instructions, or be volatile.
114 AtomicOrdering Ordering = RMWI.getOrdering();
115 assert(Ordering != AtomicOrdering::NotAtomic &&
116 Ordering != AtomicOrdering::Unordered &&
120 // ordering is compatible.
123 if (Ordering != AtomicOrdering::Release &&
124 Ordering != AtomicOrdering::Monotonic)
128 SI->setAtomic(Ordering, RMWI.getSyncScopeID());
150 // Check if the required ordering is compatible with an atomic load.
151 if (Ordering != AtomicOrdering::Acquire &
[all...] |
| /src/external/apache2/llvm/dist/llvm/include/llvm/Transforms/Utils/ |
| GlobalStatus.h | 71 /// Set to the strongest atomic ordering requirement.
72 AtomicOrdering Ordering = AtomicOrdering::NotAtomic;
|
| GlobalStatus.h | 71 /// Set to the strongest atomic ordering requirement.
72 AtomicOrdering Ordering = AtomicOrdering::NotAtomic;
|
| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/ |
| LegalizerInfo.h | 131 AtomicOrdering Ordering;
299 /// True iff the specified MMO index has at an atomic ordering of at Ordering or
302 AtomicOrdering Ordering);
|
| LegalizerInfo.h | 131 AtomicOrdering Ordering;
299 /// True iff the specified MMO index has at an atomic ordering of at Ordering or
302 AtomicOrdering Ordering);
|
| InstructionSelectorImpl.h | 383 AtomicOrdering Ordering = (AtomicOrdering)MatchTable[CurrentIdx++];
386 << InsnID << "], " << (uint64_t)Ordering << ")\n");
393 if (MMO->getOrdering() != Ordering)
400 AtomicOrdering Ordering = (AtomicOrdering)MatchTable[CurrentIdx++];
404 << InsnID << "], " << (uint64_t)Ordering << ")\n");
411 if (!isAtLeastOrStrongerThan(MMO->getOrdering(), Ordering))
418 AtomicOrdering Ordering = (AtomicOrdering)MatchTable[CurrentIdx++];
422 << InsnID << "], " << (uint64_t)Ordering << ")\n");
429 if (!isStrongerThan(Ordering, MMO->getOrdering()))
|
| InstructionSelectorImpl.h | 383 AtomicOrdering Ordering = (AtomicOrdering)MatchTable[CurrentIdx++];
386 << InsnID << "], " << (uint64_t)Ordering << ")\n");
393 if (MMO->getOrdering() != Ordering)
400 AtomicOrdering Ordering = (AtomicOrdering)MatchTable[CurrentIdx++];
404 << InsnID << "], " << (uint64_t)Ordering << ")\n");
411 if (!isAtLeastOrStrongerThan(MMO->getOrdering(), Ordering))
418 AtomicOrdering Ordering = (AtomicOrdering)MatchTable[CurrentIdx++];
422 << InsnID << "], " << (uint64_t)Ordering << ")\n");
429 if (!isStrongerThan(Ordering, MMO->getOrdering()))
|
| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| MachineMemOperand.h | 162 /// Atomic ordering requirements for this memory operation. For cmpxchg
163 /// atomic operations, atomic ordering requirements when store occurs.
164 unsigned Ordering : 4; // enum AtomicOrdering
165 /// For cmpxchg atomic operations, atomic ordering requirements when store
181 /// and atomic ordering requirements must also be specified. For cmpxchg
182 /// atomic operations the atomic ordering requirements when store does not
188 AtomicOrdering Ordering = AtomicOrdering::NotAtomic,
245 /// Return the atomic ordering requirements for this memory operation. For
246 /// cmpxchg atomic operations, return the atomic ordering requirements when
249 return static_cast<AtomicOrdering>(AtomicInfo.Ordering);
[all...] |
| MachineMemOperand.h | 162 /// Atomic ordering requirements for this memory operation. For cmpxchg
163 /// atomic operations, atomic ordering requirements when store occurs.
164 unsigned Ordering : 4; // enum AtomicOrdering
165 /// For cmpxchg atomic operations, atomic ordering requirements when store
181 /// and atomic ordering requirements must also be specified. For cmpxchg
182 /// atomic operations the atomic ordering requirements when store does not
188 AtomicOrdering Ordering = AtomicOrdering::NotAtomic,
245 /// Return the atomic ordering requirements for this memory operation. For
246 /// cmpxchg atomic operations, return the atomic ordering requirements when
249 return static_cast<AtomicOrdering>(AtomicInfo.Ordering);
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| RISCVExpandAtomicPseudoInsts.cpp | 132 static unsigned getLRForRMW32(AtomicOrdering Ordering) {
133 switch (Ordering) {
149 static unsigned getSCForRMW32(AtomicOrdering Ordering) {
150 switch (Ordering) {
166 static unsigned getLRForRMW64(AtomicOrdering Ordering) {
167 switch (Ordering) {
183 static unsigned getSCForRMW64(AtomicOrdering Ordering) {
184 switch (Ordering) {
200 static unsigned getLRForRMW(AtomicOrdering Ordering, int Width) {
202 return getLRForRMW32(Ordering);
[all...] |
| RISCVExpandAtomicPseudoInsts.cpp | 132 static unsigned getLRForRMW32(AtomicOrdering Ordering) {
133 switch (Ordering) {
149 static unsigned getSCForRMW32(AtomicOrdering Ordering) {
150 switch (Ordering) {
166 static unsigned getLRForRMW64(AtomicOrdering Ordering) {
167 switch (Ordering) {
183 static unsigned getSCForRMW64(AtomicOrdering Ordering) {
184 switch (Ordering) {
200 static unsigned getLRForRMW(AtomicOrdering Ordering, int Width) {
202 return getLRForRMW32(Ordering);
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/ |
| AArch64LegalizerInfo.cpp | 1089 auto Ordering = (*MI.memoperands_begin())->getOrdering();
1091 switch (Ordering) {
|
| AArch64LegalizerInfo.cpp | 1089 auto Ordering = (*MI.memoperands_begin())->getOrdering();
1091 switch (Ordering) {
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| SIMemoryLegalizer.cpp | 92 AtomicOrdering Ordering = AtomicOrdering::NotAtomic;
101 SIMemOpInfo(AtomicOrdering Ordering = AtomicOrdering::SequentiallyConsistent,
110 : Ordering(Ordering), FailureOrdering(FailureOrdering),
117 if (Ordering == AtomicOrdering::NotAtomic) {
130 !isStrongerThan(FailureOrdering, Ordering));
132 // There is also no cross address space ordering if the ordering
162 /// \returns Ordering constraint of the machine instruction used to
165 return Ordering;
[all...] |
| SIMemoryLegalizer.cpp | 92 AtomicOrdering Ordering = AtomicOrdering::NotAtomic;
101 SIMemOpInfo(AtomicOrdering Ordering = AtomicOrdering::SequentiallyConsistent,
110 : Ordering(Ordering), FailureOrdering(FailureOrdering),
117 if (Ordering == AtomicOrdering::NotAtomic) {
130 !isStrongerThan(FailureOrdering, Ordering));
132 // There is also no cross address space ordering if the ordering
162 /// \returns Ordering constraint of the machine instruction used to
165 return Ordering;
[all...] |
| /src/external/apache2/llvm/dist/llvm/include/llvm/Analysis/ |
| TargetTransformInfo.h | 76 // Ordering for atomic operations.
77 AtomicOrdering Ordering = AtomicOrdering::NotAtomic;
87 return (Ordering == AtomicOrdering::NotAtomic ||
88 Ordering == AtomicOrdering::Unordered) &&
410 /// TODO: Some of these could be merged. Also, a lexical ordering
|
| TargetTransformInfo.h | 76 // Ordering for atomic operations.
77 AtomicOrdering Ordering = AtomicOrdering::NotAtomic;
87 return (Ordering == AtomicOrdering::NotAtomic ||
88 Ordering == AtomicOrdering::Unordered) &&
410 /// TODO: Some of these could be merged. Also, a lexical ordering
|
| /src/external/apache2/llvm/dist/llvm/bindings/go/llvm/ |
| ir.go | 1075 func (v Value) Ordering() AtomicOrdering { return AtomicOrdering(C.LLVMGetOrdering(v.C)) }
1076 func (v Value) SetOrdering(ordering AtomicOrdering) {
1077 C.LLVMSetOrdering(v.C, C.LLVMAtomicOrdering(ordering))
1086 func (v Value) SetCmpXchgSuccessOrdering(ordering AtomicOrdering) {
1087 C.LLVMSetCmpXchgSuccessOrdering(v.C, C.LLVMAtomicOrdering(ordering))
1092 func (v Value) SetCmpXchgFailureOrdering(ordering AtomicOrdering) {
1093 C.LLVMSetCmpXchgFailureOrdering(v.C, C.LLVMAtomicOrdering(ordering))
1687 func (b Builder) CreateAtomicRMW(op AtomicRMWBinOp, ptr, val Value, ordering AtomicOrdering, singleThread bool) (v Value) {
1688 v.C = C.LLVMBuildAtomicRMW(b.C, C.LLVMAtomicRMWBinOp(op), ptr.C, val.C, C.LLVMAtomicOrdering(ordering), boolToLLVMBool(singleThread))
|
| ir.go | 1075 func (v Value) Ordering() AtomicOrdering { return AtomicOrdering(C.LLVMGetOrdering(v.C)) }
1076 func (v Value) SetOrdering(ordering AtomicOrdering) {
1077 C.LLVMSetOrdering(v.C, C.LLVMAtomicOrdering(ordering))
1086 func (v Value) SetCmpXchgSuccessOrdering(ordering AtomicOrdering) {
1087 C.LLVMSetCmpXchgSuccessOrdering(v.C, C.LLVMAtomicOrdering(ordering))
1092 func (v Value) SetCmpXchgFailureOrdering(ordering AtomicOrdering) {
1093 C.LLVMSetCmpXchgFailureOrdering(v.C, C.LLVMAtomicOrdering(ordering))
1687 func (b Builder) CreateAtomicRMW(op AtomicRMWBinOp, ptr, val Value, ordering AtomicOrdering, singleThread bool) (v Value) {
1688 v.C = C.LLVMBuildAtomicRMW(b.C, C.LLVMAtomicRMWBinOp(op), ptr.C, val.C, C.LLVMAtomicOrdering(ordering), boolToLLVMBool(singleThread))
|
| /src/external/apache2/llvm/dist/llvm/lib/Bitcode/Reader/ |
| BitcodeReader.cpp | 5006 // LOADATOMIC: [opty, op, align, vol, ordering, ssid]
5026 AtomicOrdering Ordering = getDecodedOrdering(Record[OpNum + 2]);
5027 if (Ordering == AtomicOrdering::NotAtomic ||
5028 Ordering == AtomicOrdering::Release ||
5029 Ordering == AtomicOrdering::AcquireRelease)
5031 if (Ordering != AtomicOrdering::NotAtomic && Record[OpNum] == 0)
5040 I = new LoadInst(Ty, Op, "", Record[OpNum + 1], *Align, Ordering, SSID);
5073 // STOREATOMIC: [ptrty, ptr, val, align, vol, ordering, ssid]
5088 AtomicOrdering Ordering = getDecodedOrdering(Record[OpNum + 2]);
5089 if (Ordering == AtomicOrdering::NotAtomic |
[all...] |
| BitcodeReader.cpp | 5006 // LOADATOMIC: [opty, op, align, vol, ordering, ssid]
5026 AtomicOrdering Ordering = getDecodedOrdering(Record[OpNum + 2]);
5027 if (Ordering == AtomicOrdering::NotAtomic ||
5028 Ordering == AtomicOrdering::Release ||
5029 Ordering == AtomicOrdering::AcquireRelease)
5031 if (Ordering != AtomicOrdering::NotAtomic && Record[OpNum] == 0)
5040 I = new LoadInst(Ty, Op, "", Record[OpNum + 1], *Align, Ordering, SSID);
5073 // STOREATOMIC: [ptrty, ptr, val, align, vol, ordering, ssid]
5088 AtomicOrdering Ordering = getDecodedOrdering(Record[OpNum + 2]);
5089 if (Ordering == AtomicOrdering::NotAtomic |
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/IR/ |
| Verifier.cpp | 3737 "Load cannot have Release ordering", &LI);
3765 "Store cannot have Acquire ordering", &SI);
3864 const AtomicOrdering Ordering = FI.getOrdering();
3865 Assert(Ordering == AtomicOrdering::Acquire ||
3866 Ordering == AtomicOrdering::Release ||
3867 Ordering == AtomicOrdering::AcquireRelease ||
3868 Ordering == AtomicOrdering::SequentiallyConsistent,
3870 "seq_cst ordering.",
|
| Verifier.cpp | 3737 "Load cannot have Release ordering", &LI);
3765 "Store cannot have Acquire ordering", &SI);
3864 const AtomicOrdering Ordering = FI.getOrdering();
3865 Assert(Ordering == AtomicOrdering::Acquire ||
3866 Ordering == AtomicOrdering::Release ||
3867 Ordering == AtomicOrdering::AcquireRelease ||
3868 Ordering == AtomicOrdering::SequentiallyConsistent,
3870 "seq_cst ordering.",
|
| /src/external/apache2/llvm/dist/llvm/lib/Transforms/IPO/ |
| AttributorAttributes.cpp | 1283 /// or monotonic ordering
1298 // Unordered is not a legal ordering for cmpxchg.
1303 AtomicOrdering Ordering;
1306 Ordering = cast<AtomicRMWInst>(I)->getOrdering();
1309 Ordering = cast<StoreInst>(I)->getOrdering();
1312 Ordering = cast<LoadInst>(I)->getOrdering();
1319 return (Ordering != AtomicOrdering::Unordered &&
1320 Ordering != AtomicOrdering::Monotonic);
|
