HomeSort by: relevance | last modified time | path
    Searched defs:PIdx (Results 1 - 9 of 9) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMBaseInstrInfo.h 167 int PIdx = MI.findFirstPredOperandIdx();
168 return PIdx != -1 ? (ARMCC::CondCodes)MI.getOperand(PIdx).getImm()
ARMBaseRegisterInfo.cpp 826 int PIdx = MI.findFirstPredOperandIdx();
827 ARMCC::CondCodes Pred = (PIdx == -1)
828 ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
829 Register PredReg = (PIdx == -1) ? Register() : MI.getOperand(PIdx+1).getReg();
MVETPAndVPTOptimisationsPass.cpp 890 int PIdx = llvm::findFirstVPTPredOperandIdx(Instr);
891 if (PIdx == -1)
893 Register VPR = Instr.getOperand(PIdx + 1).getReg();
923 Instr.getOperand(PIdx + 1).setReg(LastVPTReg);
940 Instr.getOperand(PIdx + 1).setReg(NewVPR);
ARMLowOverheadLoops.cpp 83 int PIdx = llvm::findFirstVPTPredOperandIdx(*MI);
84 return PIdx != -1 && MI->getOperand(PIdx + 1).getReg() == ARM::VPR;
1446 int PIdx = llvm::findFirstVPTPredOperandIdx(*MI);
1447 assert(PIdx >= 1 && "Trying to unpredicate a non-predicated instruction");
1448 assert(MI->getOperand(PIdx).getImm() == ARMVCC::Then &&
1450 MI->getOperand(PIdx).setImm(ARMVCC::None);
1451 MI->getOperand(PIdx + 1).setReg(0);
ARMFrameLowering.cpp 2311 int PIdx = Old.findFirstPredOperandIdx();
2313 (PIdx == -1) ? ARMCC::AL
2314 : (ARMCC::CondCodes)Old.getOperand(PIdx).getImm();
ARMBaseInstrInfo.cpp 537 int PIdx = I->findFirstPredOperandIdx();
538 if (PIdx != -1 && I->getOperand(PIdx).getImm() != ARMCC::AL)
544 int PIdx = MI.findFirstPredOperandIdx();
545 return PIdx != -1 && MI.getOperand(PIdx).getImm() != ARMCC::AL;
584 int PIdx = MI.findFirstPredOperandIdx();
585 if (PIdx != -1) {
586 MachineOperand &PMO = MI.getOperand(PIdx);
588 MI.getOperand(PIdx+1).setReg(Pred[1].getReg())
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
InlineSpiller.cpp 1286 SlotIndex PIdx = LIS.getInstructionIndex(*PrevSpill);
1288 MachineInstr *SpillToRm = (CIdx > PIdx) ? CurrentSpill : PrevSpill;
1289 MachineInstr *SpillToKeep = (CIdx > PIdx) ? PrevSpill : CurrentSpill;
MachineScheduler.cpp 2032 unsigned PIdx = PI->ProcResourceIdx;
2033 unsigned Factor = SchedModel->getResourceFactor(PIdx);
2034 RemainingCounts[PIdx] += (Factor * PI->Cycles);
2102 SchedBoundary::getNextResourceCycle(const MCSchedClassDesc *SC, unsigned PIdx,
2107 unsigned StartIndex = ReservedCyclesIndex[PIdx];
2108 unsigned NumberOfInstances = SchedModel->getProcResource(PIdx)->NumUnits;
2112 if (isUnbufferedGroup(PIdx)) {
2125 if (ResourceGroupSubUnitMasks[PIdx][PE.ProcResourceIdx])
2128 auto SubUnits = SchedModel->getProcResource(PIdx)->SubUnitsIdxBegin;
2242 for (unsigned PIdx = 1, PEnd = SchedModel->getNumProcResourceKinds()
    [all...]
  /src/external/apache2/llvm/dist/llvm/utils/TableGen/
CodeGenSchedule.cpp 1243 for (unsigned PIdx = 0, PEnd = ProcModels.size(); PIdx != PEnd; ++PIdx) {
1244 const CodeGenProcModel &PM = ProcModels[PIdx];
1258 inferFromRW(Writes, Reads, FromClassIdx, PIdx);
1280 unsigned PIdx = getProcModel(Rec->getValueAsDef("SchedModel")).Index;
1281 inferFromRW(Writes, Reads, SCIdx, PIdx); // May mutate SchedClasses.
1282 SchedClasses[SCIdx].InstRWProcIndices.insert(PIdx);
1891 unsigned PIdx = getProcModel(RWModelDef).Index;
1894 collectRWResources(Writes, Reads, PIdx);
    [all...]

Completed in 70 milliseconds