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    Searched defs:ShiftImm (Results 1 - 9 of 9) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
AArch64PostLegalizerCombiner.cpp 255 int64_t ShiftImm;
258 m_OneNonDBGUse(m_any_of(m_GAShr(m_Reg(ShiftSrc), m_ICst(ShiftImm)),
259 m_GLShr(m_Reg(ShiftSrc), m_ICst(ShiftImm))))))
261 if (ShiftImm < 0 || ShiftImm + Width > Ty.getSizeInBits())
264 auto Cst1 = B.buildConstant(Ty, ShiftImm);
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsExpandPseudo.cpp 181 const unsigned ShiftImm =
185 .addImm(ShiftImm);
188 .addImm(ShiftImm);
557 const unsigned ShiftImm = SEOp == Mips::SEH ? 16 : 24;
560 .addImm(ShiftImm);
563 .addImm(ShiftImm);
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/MCTargetDesc/
ARMMCCodeEmitter.cpp 947 // This value is encoded as follows, if ShiftImm is the value within those
948 // ranges then the encoding szimm5 = ShiftImm + size, where size is either 8
951 unsigned Size, ShiftImm;
968 ShiftImm = MI.getOperand(OpIdx).getImm();
969 return Size + ShiftImm;
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCMIPeephole.cpp 666 unsigned ShiftImm = DefMI->getOperand(3).getImm();
669 unsigned NewElem = (SplatImm + ShiftImm) & 0x3;
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64FastISel.cpp 212 uint64_t ShiftImm, bool SetFlags = false,
216 uint64_t ShiftImm, bool SetFlags = false,
243 AArch64_AM::ShiftExtendType ShiftType, uint64_t ShiftImm,
250 unsigned RHSReg, uint64_t ShiftImm);
1325 unsigned ShiftImm;
1327 ShiftImm = 0;
1329 ShiftImm = 12;
1358 .addImm(getShifterImm(AArch64_AM::LSL, ShiftImm));
1365 uint64_t ShiftImm, bool SetFlags,
1375 if (ShiftImm >= RetVT.getSizeInBits()
    [all...]
AArch64ISelDAGToDAG.cpp 1871 uint64_t ShiftImm;
1872 if (!isOpcWithIntImmediate(Op.getNode(), ISD::SRL, ShiftImm) &&
1873 !isOpcWithIntImmediate(Op.getNode(), ISD::SRA, ShiftImm))
1877 if (ShiftImm + Width > BitWidth)
1882 Immr = ShiftImm;
1883 Imms = ShiftImm + Width - 1;
1895 // SRL Value2, ShiftImm
1897 // with MaskImm >> ShiftImm to search for the bit width.
1901 // UBFM Value, ShiftImm, BitWide + SrlImm -1
2008 uint64_t ShiftImm;
    [all...]
AArch64ISelLowering.cpp 14665 unsigned ShiftImm = N->getConstantOperandVal(1);
14666 assert(OpScalarSize > ShiftImm && "Invalid shift imm");
14668 APInt ShiftedOutBits = APInt::getLowBitsSet(OpScalarSize, ShiftImm);
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMFastISel.cpp 2775 unsigned ShiftImm;
2778 ShiftImm = CI->getZExtValue();
2782 if (ShiftImm == 0 || ShiftImm >=32)
2806 MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, ShiftImm));
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/AsmParser/
ARMAsmParser.cpp 853 unsigned ShiftImm; // shift for OffsetReg.
863 unsigned ShiftImm;
875 unsigned ShiftImm;
881 unsigned ShiftImm;
1691 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
1710 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
1889 (Memory.ShiftType != ARM_AM::uxtw || Memory.ShiftImm != shift))
2551 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
2560 unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm);
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