| /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.h | 634 SDValue combineExtract(const SDLoc &DL, EVT ElemVT, EVT VecVT, SDValue OrigOp,
721 MVT VecVT;
|
| SystemZISelLowering.cpp | 737 VecVT = MVT::getVectorVT(MVT::getIntegerVT(8), 16);
750 VecVT = MVT::getVectorVT(MVT::getIntegerVT(SplatBitSize),
763 VecVT = MVT::getVectorVT(MVT::getIntegerVT(SplatBitSize),
5249 EVT VecVT = Op0.getValueType();
5254 unsigned Mask = VecVT.getVectorNumElements() - 1;
5261 MVT IntVecVT = MVT::getVectorVT(IntVT, VecVT.getVectorNumElements());
5718 // Try to simplify an EXTRACT_VECTOR_ELT from a vector of type VecVT
5720 // of the input vector and Index is the index (based on type VecVT) that
5724 EVT VecVT, SDValue Op,
5731 unsigned BytesPerElement = VecVT.getVectorElementType().getStoreSize()
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeTypesGeneric.cpp | 373 EVT VecVT = N->getValueType(0);
374 unsigned NumElts = VecVT.getVectorNumElements();
379 assert(OldVT == VecVT.getVectorElementType() &&
400 return DAG.getNode(ISD::BITCAST, dl, VecVT, NewVec);
411 EVT VecVT = N->getValueType(0);
412 unsigned NumElts = VecVT.getVectorNumElements();
419 assert(OldEVT == VecVT.getVectorElementType() &&
442 return DAG.getNode(ISD::BITCAST, dl, VecVT, NewVec);
|
| LegalizeFloatTypes.cpp | 2333 EVT VecVT = Vec->getValueType(0);
2334 EVT EltVT = VecVT.getVectorElementType();
2338 switch (getTypeAction(VecVT)) {
|
| LegalizeIntegerTypes.cpp | 1695 EVT VecVT = N->getValueType(0);
1696 unsigned NumElts = VecVT.getVectorNumElements();
1697 assert(!((NumElts & 1) && (!TLI.isTypeLegal(VecVT))) &&
|
| LegalizeVectorTypes.cpp | 1277 EVT VecVT = Vec.getValueType();
1280 unsigned VecElems = VecVT.getVectorMinNumElements();
1295 if (VecVT.isScalableVector() == SubVecVT.isScalableVector() &&
1305 Align SmallestAlign = DAG.getReducedAlign(VecVT, /*UseABI=*/false);
1307 DAG.CreateStackTemporary(VecVT.getStoreSize(), SmallestAlign);
1316 SDValue SubVecPtr = TLI.getVectorElementPointer(DAG, StackPtr, VecVT, Idx);
1517 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, ResNE);
1518 return DAG.getBuildVector(VecVT, dl, Scalars);
1591 EVT VecVT = Vec.getValueType();
1592 EVT EltVT = VecVT.getVectorElementType()
[all...] |
| TargetLowering.cpp | 824 EVT VecVT = Vec.getValueType();
825 if (CIdx && CIdx->getAPIntValue().ult(VecVT.getVectorNumElements()) &&
1009 EVT VecVT = Vec.getValueType();
1014 if (CIdx && CIdx->getAPIntValue().ult(VecVT.getVectorNumElements())) {
7777 EVT VecVT,
7779 if (!VecVT.isScalableVector() && isa<ConstantSDNode>(Idx))
7783 unsigned NElts = VecVT.getVectorMinNumElements();
7784 if (VecVT.isScalableVector()) {
7806 SDValue VecPtr, EVT VecVT,
7812 EVT EltVT = VecVT.getVectorElementType()
[all...] |
| DAGCombiner.cpp | 18511 EVT VecVT = VecOp.getValueType();
18523 return VecVT.isInteger() ? DAG.getAnyExtOrTrunc(Elt, DL, ScalarVT) : Elt;
18545 if (IndexC && VecVT.isFixedLengthVector() &&
18546 IndexC->getAPIntValue().uge(VecVT.getVectorNumElements()))
18552 TLI.isTypeLegal(VecVT) &&
18553 (VecOp.hasOneUse() || TLI.aggressivelyPreferBuildVectorSources(VecVT))) {
18555 VecVT.isFixedLengthVector()) &&
18570 if (VecVT.isScalableVector())
18576 unsigned NumElts = VecVT.getVectorNumElements();
18577 unsigned VecEltBitWidth = VecVT.getScalarSizeInBits()
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| R600ISelLowering.cpp | 675 EVT VecVT = Vector.getValueType();
676 EVT EltVT = VecVT.getVectorElementType();
679 for (unsigned i = 0, e = VecVT.getVectorNumElements(); i != e; ++i) {
684 return DAG.getNode(AMDGPUISD::BUILD_VERTICAL_VECTOR, DL, VecVT, Args);
|
| SIISelLowering.cpp | 5376 EVT VecVT = Vec.getValueType();
5378 EVT EltVT = VecVT.getVectorElementType();
5386 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, SL, VecVT, Vec, Elt,
5397 EVT VecVT = Vec.getValueType();
5398 EVT EltVT = VecVT.getVectorElementType();
5399 unsigned VecSize = VecVT.getSizeInBits();
5405 unsigned NumElts = VecVT.getVectorNumElements();
5433 return DAG.getNode(ISD::BITCAST, SL, VecVT, Concat);
5447 DAG.getSplatBuildVector(VecVT, SL, InsVal));
5465 return DAG.getNode(ISD::BITCAST, SL, VecVT, BFI)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | 2567 EVT VecVT = EVT::getVectorVT(F->getContext(), LoadVT, NumElts);
2574 DAG.getLoad(VecVT, dl, Root, VecAddr,
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| ARMISelDAGToDAG.cpp | 4117 EVT VecVT = N->getValueType(0);
4118 EVT EltVT = VecVT.getVectorElementType();
4119 unsigned NumElts = VecVT.getVectorNumElements();
4123 N, createDRegPairNode(VecVT, N->getOperand(0), N->getOperand(1)));
4129 N, createSRegPairNode(VecVT, N->getOperand(0), N->getOperand(1)));
4134 createQuadSRegsNode(VecVT, N->getOperand(0), N->getOperand(1),
|
| ARMISelLowering.cpp | 5926 EVT VecVT = EVT::getVectorVT(
5929 SDValue BitCast = DAG.getNode(ISD::BITCAST, dl, VecVT, ExtractSrc);
7632 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), IVT, NumElts);
7633 SDValue Val = DAG.getBuildVector(VecVT, dl, Ops);
7690 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
7694 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, Ops);
8506 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
8507 V1 = DAG.getNode(ISD::BITCAST, dl, VecVT, V1);
8508 V2 = DAG.getNode(ISD::BITCAST, dl, VecVT, V2);
8519 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, Ops)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86ISelDAGToDAG.cpp | 424 MVT VecVT = N->getOperand(0).getSimpleValueType();
425 return getI8Imm((Index * VecVT.getScalarSizeInBits()) / VecWidth, DL);
432 MVT VecVT = N->getSimpleValueType(0);
433 return getI8Imm((Index * VecVT.getScalarSizeInBits()) / VecWidth, DL);
1124 MVT VecVT = VT == MVT::f64 ? MVT::v2f64 : MVT::v4f32;
1126 SDValue Op0 = CurDAG->getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT,
1128 SDValue Op1 = CurDAG->getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT,
1133 EVT IntVT = EVT(VecVT).changeVectorElementTypeToInteger();
1145 Res = CurDAG->getNode(ISD::BITCAST, dl, VecVT, Res);
1147 Res = CurDAG->getNode(N->getOpcode(), dl, VecVT, Op0, Op1)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| RISCVISelLowering.cpp | 1111 // Attempt to decompose a subvector insert/extract between VecVT and
1118 MVT VecVT, MVT SubVecVT, unsigned InsertExtractIdx,
1124 unsigned VecRegClassID = getRegClassIDForVecVT(VecVT);
1136 VecVT = VecVT.getHalfNumVectorElementsVT();
1138 InsertExtractIdx >= VecVT.getVectorElementCount().getKnownMinValue();
1140 getSubregIndexByMVT(VecVT, IsHi));
1142 InsertExtractIdx -= VecVT.getVectorElementCount().getKnownMinValue();
1276 // VecVT is a vector type, either fixed-length or scalable, and ContainerVT is
1279 getDefaultVLOps(MVT VecVT, MVT ContainerVT, SDLoc DL, SelectionDAG &DAG
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 8311 EVT VecVT = Vec.getValueType();
8312 assert(VecVT.isVector() && "Expected a vector type.");
8313 assert(VecVT.getSizeInBits() < 128 && "Vector is already full width.");
8315 EVT EltVT = VecVT.getVectorElementType();
8319 unsigned NumConcat = WideNumElts / VecVT.getVectorNumElements();
8322 SDValue UndefVec = DAG.getUNDEF(VecVT);
8916 EVT VecVT = V->getValueType(0);
8917 bool RightType = VecVT == MVT::v2f64 ||
8918 (HasP8Vector && VecVT == MVT::v4f32) ||
8919 (HasDirectMove && (VecVT == MVT::v2i64 || VecVT == MVT::v4i32))
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 6736 EVT VecVT;
6742 VecVal1 = DAG.getTargetInsertSubreg(Idx, DL, VecVT,
6743 DAG.getUNDEF(VecVT), In1);
6744 VecVal2 = DAG.getTargetInsertSubreg(Idx, DL, VecVT,
6745 DAG.getUNDEF(VecVT), In2);
6747 VecVal1 = DAG.getNode(ISD::BITCAST, DL, VecVT, In1);
6748 VecVal2 = DAG.getNode(ISD::BITCAST, DL, VecVT, In2);
6753 VecVT = (VT == MVT::v2f32 ? MVT::v2i32 : MVT::v4i32);
6757 VecVT = MVT::v2i64;
6766 VecVT = (VT == MVT::v4f16 ? MVT::v4i16 : MVT::v8i16)
[all...] |
