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    Searched defs:VectorSize (Results 1 - 6 of 6) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonAsmPrinter.cpp 247 unsigned VectorSize, MCContext &Ctx) {
258 auto *NewCE = MCConstantExpr::create(V / int32_t(VectorSize), Ctx);
271 unsigned VectorSize = HRI.getRegSizeInBits(Hexagon::HvxVRRegClass) / 8;
638 MappedInst = ScaleVectorOffset(Inst, 3, VectorSize, OutContext);
648 MappedInst = ScaleVectorOffset(Inst, 2, VectorSize, OutContext);
656 MappedInst = ScaleVectorOffset(Inst, 2, VectorSize, OutContext);
664 MappedInst = ScaleVectorOffset(Inst, 1, VectorSize, OutContext);
679 MappedInst = ScaleVectorOffset(Inst, 4, VectorSize, OutContext);
694 MappedInst = ScaleVectorOffset(Inst, 3, VectorSize, OutContext);
711 MappedInst = ScaleVectorOffset(Inst, 3, VectorSize, OutContext)
    [all...]
HexagonInstrInfo.cpp 2731 unsigned VectorSize = TRI->getSpillSize(Hexagon::HvxVRRegClass);
2732 assert(isPowerOf2_32(VectorSize));
2733 if (Offset & (VectorSize-1))
2735 return isInt<4>(Offset >> Log2_32(VectorSize));
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86InterleavedAccess.cpp 436 // VectorSize = 128 => Lane = 1
437 // VectorSize = 256 => Lane = 2
442 int VectorSize = VT.getSizeInBits();
444 int LaneCount = std::max(VectorSize / 128, 1);
455 int VectorSize = VT.getSizeInBits();
456 int VF = VT.getVectorNumElements() / std::max(VectorSize / 128, 1);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPULibFunc.h 293 unsigned char VectorSize;
300 VectorSize = 1;
  /src/external/apache2/llvm/dist/llvm/bindings/go/llvm/
ir.go 691 func (t Type) VectorSize() int { return int(C.LLVMGetVectorSize(t.C)) }
  /src/external/apache2/llvm/dist/clang/lib/Sema/
TreeTransform.h 14274 IntegerLiteral *VectorSize
14277 return SemaRef.BuildExtVectorType(ElementType, VectorSize, AttributeLoc);

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