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    Searched defs:VectorWidth (Results 1 - 8 of 8) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
MVETailPredication.cpp 194 // ceil(ElementCount / VectorWidth) >= TripCount
196 // ((ElementCount + (VectorWidth - 1)) / VectorWidth
198 // (((ElementCount + (VectorWidth - 1)) / VectorWidth) - TripCount
214 int VectorWidth =
216 if (VectorWidth != 4 && VectorWidth != 8 && VectorWidth != 16)
242 (ConstElemCount->getZExtValue() + VectorWidth - 1) / VectorWidth
    [all...]
MVETailPredication.cpp 194 // ceil(ElementCount / VectorWidth) >= TripCount
196 // ((ElementCount + (VectorWidth - 1)) / VectorWidth
198 // (((ElementCount + (VectorWidth - 1)) / VectorWidth) - TripCount
214 int VectorWidth =
216 if (VectorWidth != 4 && VectorWidth != 8 && VectorWidth != 16)
242 (ConstElemCount->getZExtValue() + VectorWidth - 1) / VectorWidth
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/Scalar/
ScalarizeMaskedMemIntrin.cpp 108 static unsigned adjustForEndian(const DataLayout &DL, unsigned VectorWidth,
110 return DL.isBigEndian() ? VectorWidth - 1 - Idx : Idx;
179 unsigned VectorWidth = cast<FixedVectorType>(VecType)->getNumElements();
185 for (unsigned Idx = 0; Idx < VectorWidth; ++Idx) {
200 if (VectorWidth != 1) {
201 Type *SclrMaskTy = Builder.getIntNTy(VectorWidth);
205 for (unsigned Idx = 0; Idx < VectorWidth; ++Idx) {
214 if (VectorWidth != 1) {
216 VectorWidth, adjustForEndian(DL, VectorWidth, Idx)))
    [all...]
ScalarizeMaskedMemIntrin.cpp 108 static unsigned adjustForEndian(const DataLayout &DL, unsigned VectorWidth,
110 return DL.isBigEndian() ? VectorWidth - 1 - Idx : Idx;
179 unsigned VectorWidth = cast<FixedVectorType>(VecType)->getNumElements();
185 for (unsigned Idx = 0; Idx < VectorWidth; ++Idx) {
200 if (VectorWidth != 1) {
201 Type *SclrMaskTy = Builder.getIntNTy(VectorWidth);
205 for (unsigned Idx = 0; Idx < VectorWidth; ++Idx) {
214 if (VectorWidth != 1) {
216 VectorWidth, adjustForEndian(DL, VectorWidth, Idx)))
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86InterleavedAccess.cpp 614 int VectorWidth = VT.getSizeInBits();
617 int Lane = (VectorWidth / 128 > 0) ? VectorWidth / 128 : 1;
X86InterleavedAccess.cpp 614 int VectorWidth = VT.getSizeInBits();
617 int Lane = (VectorWidth / 128 > 0) ? VectorWidth / 128 : 1;
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
IRTranslator.cpp 1470 unsigned VectorWidth = 0;
1472 VectorWidth = cast<FixedVectorType>(VT)->getNumElements();
1476 if (VectorWidth && !PtrTy.isVector()) {
1478 MIRBuilder.buildSplatVector(LLT::vector(VectorWidth, PtrTy), BaseReg)
1480 PtrIRTy = FixedVectorType::get(PtrIRTy, VectorWidth);
1514 if (!IdxTy.isVector() && VectorWidth) {
IRTranslator.cpp 1470 unsigned VectorWidth = 0;
1472 VectorWidth = cast<FixedVectorType>(VT)->getNumElements();
1476 if (VectorWidth && !PtrTy.isVector()) {
1478 MIRBuilder.buildSplatVector(LLT::vector(VectorWidth, PtrTy), BaseReg)
1480 PtrIRTy = FixedVectorType::get(PtrIRTy, VectorWidth);
1514 if (!IdxTy.isVector() && VectorWidth) {

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