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    Searched defs:allowed_mclk_vdd_table (Results 1 - 8 of 8) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
amdgpu_vega10_hwmgr.c	779 struct phm_ppt_v1_clock_voltage_dependency_table *allowed_mclk_vdd_table = local in function:vega10_set_private_data_based_on_pptable 787 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table, 789 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1, 795 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk; 799 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci;
amdgpu_smu7_hwmgr.c	2084 struct phm_ppt_v1_clock_voltage_dependency_table *allowed_mclk_vdd_table = local in function:smu7_set_private_data_based_on_pptable_v1 2094 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table != NULL, 2097 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1, 2104 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk; 2108 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci;
amdgpu_vega10_hwmgr.c	779 struct phm_ppt_v1_clock_voltage_dependency_table *allowed_mclk_vdd_table = local in function:vega10_set_private_data_based_on_pptable 787 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table, 789 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1, 795 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk; 799 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci;
amdgpu_smu7_hwmgr.c	2084 struct phm_ppt_v1_clock_voltage_dependency_table *allowed_mclk_vdd_table = local in function:smu7_set_private_data_based_on_pptable_v1 2094 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table != NULL, 2097 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1, 2104 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk; 2108 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci;
amdgpu_vega10_hwmgr.c	779 struct phm_ppt_v1_clock_voltage_dependency_table *allowed_mclk_vdd_table = local in function:vega10_set_private_data_based_on_pptable 787 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table, 789 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1, 795 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk; 799 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci;
amdgpu_smu7_hwmgr.c	2084 struct phm_ppt_v1_clock_voltage_dependency_table *allowed_mclk_vdd_table = local in function:smu7_set_private_data_based_on_pptable_v1 2094 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table != NULL, 2097 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1, 2104 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk; 2108 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci;
amdgpu_vega10_hwmgr.c	779 struct phm_ppt_v1_clock_voltage_dependency_table *allowed_mclk_vdd_table = local in function:vega10_set_private_data_based_on_pptable 787 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table, 789 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1, 795 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk; 799 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci;
amdgpu_smu7_hwmgr.c	2084 struct phm_ppt_v1_clock_voltage_dependency_table *allowed_mclk_vdd_table = local in function:smu7_set_private_data_based_on_pptable_v1 2094 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table != NULL, 2097 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1, 2104 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk; 2108 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci;

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Indexes created Tue Sep 30 11:09:46 GMT 2025