/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/calcs/ |
amdgpu_dcn_calcs.c | 735 int vesa_sync_start, asic_blank_end, asic_blank_start; local in function:dcn_validate_bandwidth 1199 asic_blank_start = asic_blank_end + 1205 pipe->pipe_dlg_param.vblank_start = asic_blank_start;
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amdgpu_dcn_calcs.c | 735 int vesa_sync_start, asic_blank_end, asic_blank_start; local in function:dcn_validate_bandwidth 1199 asic_blank_start = asic_blank_end + 1205 pipe->pipe_dlg_param.vblank_start = asic_blank_start;
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amdgpu_dcn_calcs.c | 735 int vesa_sync_start, asic_blank_end, asic_blank_start; local in function:dcn_validate_bandwidth 1199 asic_blank_start = asic_blank_end + 1205 pipe->pipe_dlg_param.vblank_start = asic_blank_start;
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amdgpu_dcn_calcs.c | 735 int vesa_sync_start, asic_blank_end, asic_blank_start; local in function:dcn_validate_bandwidth 1199 asic_blank_start = asic_blank_end + 1205 pipe->pipe_dlg_param.vblank_start = asic_blank_start;
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amdgpu_dcn_calcs.c | 735 int vesa_sync_start, asic_blank_end, asic_blank_start; local in function:dcn_validate_bandwidth 1199 asic_blank_start = asic_blank_end + 1205 pipe->pipe_dlg_param.vblank_start = asic_blank_start;
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/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
amdgpu_dcn10_optc.c | 156 uint32_t asic_blank_start; local in function:optc1_program_timing 186 asic_blank_start = patched_crtc_timing.h_total - 190 asic_blank_end = asic_blank_start - 196 OTG_H_BLANK_START, asic_blank_start, 227 asic_blank_start = patched_crtc_timing.v_total - 231 asic_blank_end = asic_blank_start - 237 OTG_V_BLANK_START, asic_blank_start,
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amdgpu_dcn10_optc.c | 156 uint32_t asic_blank_start; local in function:optc1_program_timing 186 asic_blank_start = patched_crtc_timing.h_total - 190 asic_blank_end = asic_blank_start - 196 OTG_H_BLANK_START, asic_blank_start, 227 asic_blank_start = patched_crtc_timing.v_total - 231 asic_blank_end = asic_blank_start - 237 OTG_V_BLANK_START, asic_blank_start,
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amdgpu_dcn10_optc.c | 156 uint32_t asic_blank_start; local in function:optc1_program_timing 186 asic_blank_start = patched_crtc_timing.h_total - 190 asic_blank_end = asic_blank_start - 196 OTG_H_BLANK_START, asic_blank_start, 227 asic_blank_start = patched_crtc_timing.v_total - 231 asic_blank_end = asic_blank_start - 237 OTG_V_BLANK_START, asic_blank_start,
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amdgpu_dcn10_optc.c | 156 uint32_t asic_blank_start; local in function:optc1_program_timing 186 asic_blank_start = patched_crtc_timing.h_total - 190 asic_blank_end = asic_blank_start - 196 OTG_H_BLANK_START, asic_blank_start, 227 asic_blank_start = patched_crtc_timing.v_total - 231 asic_blank_end = asic_blank_start - 237 OTG_V_BLANK_START, asic_blank_start,
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amdgpu_dcn10_optc.c | 156 uint32_t asic_blank_start; local in function:optc1_program_timing 186 asic_blank_start = patched_crtc_timing.h_total - 190 asic_blank_end = asic_blank_start - 196 OTG_H_BLANK_START, asic_blank_start, 227 asic_blank_start = patched_crtc_timing.v_total - 231 asic_blank_end = asic_blank_start - 237 OTG_V_BLANK_START, asic_blank_start,
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