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    Searched defs:cfg (Results 1 - 25 of 176) sorted by relevancy

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  /src/usr.sbin/bthcid/
config.c 97 prop_dictionary_t cfg; local in function:lookup_key
100 cfg = load_keys();
101 if (cfg == NULL)
104 obj = prop_dictionary_get(cfg, bt_ntoa(laddr, NULL));
106 prop_object_release(cfg);
113 prop_object_release(cfg);
118 prop_object_release(cfg);
125 prop_dictionary_t cfg, dev; local in function:save_key
131 cfg = load_keys();
132 if (cfg == NULL)
    [all...]
config.c 97 prop_dictionary_t cfg; local in function:lookup_key
100 cfg = load_keys();
101 if (cfg == NULL)
104 obj = prop_dictionary_get(cfg, bt_ntoa(laddr, NULL));
106 prop_object_release(cfg);
113 prop_object_release(cfg);
118 prop_object_release(cfg);
125 prop_dictionary_t cfg, dev; local in function:save_key
131 cfg = load_keys();
132 if (cfg == NULL)
    [all...]
  /src/sys/arch/arm/imx/
imx_genfb.c 88 prop_dictionary_t cfg = device_properties(self); local in function:imx_genfb_attach
96 prop_dictionary_set_uint32(cfg, "width", ifb->ifb_width);
97 prop_dictionary_set_uint32(cfg, "height", ifb->ifb_height);
98 prop_dictionary_set_uint8(cfg, "depth", ifb->ifb_depth);
99 prop_dictionary_set_uint16(cfg, "linebytes", ifb->ifb_stride);
100 prop_dictionary_set_uint32(cfg, "address", 0);
101 prop_dictionary_set_uint32(cfg, "virtual_address",
120 prop_dictionary_get_bool(cfg, "is_console", &is_console);
imx_genfb.c 88 prop_dictionary_t cfg = device_properties(self); local in function:imx_genfb_attach
96 prop_dictionary_set_uint32(cfg, "width", ifb->ifb_width);
97 prop_dictionary_set_uint32(cfg, "height", ifb->ifb_height);
98 prop_dictionary_set_uint8(cfg, "depth", ifb->ifb_depth);
99 prop_dictionary_set_uint16(cfg, "linebytes", ifb->ifb_stride);
100 prop_dictionary_set_uint32(cfg, "address", 0);
101 prop_dictionary_set_uint32(cfg, "virtual_address",
120 prop_dictionary_get_bool(cfg, "is_console", &is_console);
  /src/sys/dev/isa/
weasel_isa.c 78 struct weasel_config_block cfg; local in function:weasel_isa_init
118 WEASEL_CONFIG_BLOCK, &cfg, sizeof(cfg));
122 for (cp = (u_int8_t *)&cfg, j = 0, sum = 1;
123 j < (sizeof(cfg) - 1); j++)
125 if (sum == cfg.cksum)
129 if (sum != cfg.cksum) {
136 sum, cfg.cksum);
140 switch (cfg.cfg_version) {
143 switch (cfg.enable_duart_switching)
    [all...]
weasel_isa.c 78 struct weasel_config_block cfg; local in function:weasel_isa_init
118 WEASEL_CONFIG_BLOCK, &cfg, sizeof(cfg));
122 for (cp = (u_int8_t *)&cfg, j = 0, sum = 1;
123 j < (sizeof(cfg) - 1); j++)
125 if (sum == cfg.cksum)
129 if (sum != cfg.cksum) {
136 sum, cfg.cksum);
140 switch (cfg.cfg_version) {
143 switch (cfg.enable_duart_switching)
    [all...]
  /src/sys/dev/pci/
iteide.c 102 pcireg_t cfg, modectl; local in function:ite_chip_map
108 cfg = pci_conf_read(sc->sc_pc, sc->sc_tag, IT_CFG);
110 ATADEBUG_PRINT(("%s: cfg=0x%x, modectl=0x%x\n",
111 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), cfg & IT_CFG_MASK,
155 cfg = pci_conf_read(sc->sc_pc, sc->sc_tag, IT_CFG);
157 ATADEBUG_PRINT(("%s: cfg=0x%x, modectl=0x%x\n",
158 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), cfg & IT_CFG_MASK,
171 pcireg_t cfg, modectl; local in function:ite_setup_channel
174 cfg = pci_conf_read(sc->sc_pc, sc->sc_tag, IT_CFG);
204 (cfg & IT_CFG_CABLE(channel, drive)) == 0)
    [all...]
iteide.c 102 pcireg_t cfg, modectl; local in function:ite_chip_map
108 cfg = pci_conf_read(sc->sc_pc, sc->sc_tag, IT_CFG);
110 ATADEBUG_PRINT(("%s: cfg=0x%x, modectl=0x%x\n",
111 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), cfg & IT_CFG_MASK,
155 cfg = pci_conf_read(sc->sc_pc, sc->sc_tag, IT_CFG);
157 ATADEBUG_PRINT(("%s: cfg=0x%x, modectl=0x%x\n",
158 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), cfg & IT_CFG_MASK,
171 pcireg_t cfg, modectl; local in function:ite_setup_channel
174 cfg = pci_conf_read(sc->sc_pc, sc->sc_tag, IT_CFG);
204 (cfg & IT_CFG_CABLE(channel, drive)) == 0)
    [all...]
weasel_pci.c 102 struct weasel_config_block cfg; local in function:weasel_pci_attach
141 if (++cfg_size != sizeof(cfg)) {
147 for (cp = (uint8_t *) &cfg; cfg_size != 0; cfg_size--) {
158 switch (cfg.cfg_version) {
161 switch (cfg.enable_duart_switching) {
184 device_xname(self), cfg.cfg_version);
247 cfg.break_passthru ? "enabled" : "disabled");
253 sc->sc_wdog_period = be16toh(cfg.wdt_msec) / 1000;
  /src/sys/arch/macppc/dev/
smuiic.c 79 prop_array_t cfg; local in function:smuiic_attach
89 cfg = prop_array_create();
90 prop_dictionary_set(dict, "i2c-child-devices", cfg);
91 prop_object_release(cfg);
116 prop_array_add(cfg, dev);
smuiic.c 79 prop_array_t cfg; local in function:smuiic_attach
89 cfg = prop_array_create();
90 prop_dictionary_set(dict, "i2c-child-devices", cfg);
91 prop_object_release(cfg);
116 prop_array_add(cfg, dev);
  /src/sys/dev/mii/
lxtphy.c 294 uint16_t cfg; local in function:lxtphy_set_tp
296 PHY_READ(sc, MII_LXTPHY_CONFIG, &cfg);
297 cfg &= ~CONFIG_100BASEFX;
298 PHY_WRITE(sc, MII_LXTPHY_CONFIG, cfg);
304 uint16_t cfg; local in function:lxtphy_set_fx
306 PHY_READ(sc, MII_LXTPHY_CONFIG, &cfg);
307 cfg |= CONFIG_100BASEFX;
308 PHY_WRITE(sc, MII_LXTPHY_CONFIG, cfg);
lxtphy.c 294 uint16_t cfg; local in function:lxtphy_set_tp
296 PHY_READ(sc, MII_LXTPHY_CONFIG, &cfg);
297 cfg &= ~CONFIG_100BASEFX;
298 PHY_WRITE(sc, MII_LXTPHY_CONFIG, cfg);
304 uint16_t cfg; local in function:lxtphy_set_fx
306 PHY_READ(sc, MII_LXTPHY_CONFIG, &cfg);
307 cfg |= CONFIG_100BASEFX;
308 PHY_WRITE(sc, MII_LXTPHY_CONFIG, cfg);
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
amdgpu_dcn20_link_encoder.c 214 struct dpcssys_phy_seq_cfg *cfg)
218 cfg->load_sram_fw = false;
221 cfg->lane_en[i] = true;
225 cfg->mpll_cfg = dcn2_mpll_cfg[0];
228 cfg->mpll_cfg = dcn2_mpll_cfg[1];
231 cfg->mpll_cfg = dcn2_mpll_cfg[2];
234 cfg->mpll_cfg = dcn2_mpll_cfg[3];
252 struct dpcssys_phy_seq_cfg *cfg = &enc20->phy_seq_cfg; local in function:dcn20_link_encoder_enable_dp_output
259 if (!update_cfg_data(enc10, link_settings, cfg))
amdgpu_dcn20_link_encoder.c 214 struct dpcssys_phy_seq_cfg *cfg)
218 cfg->load_sram_fw = false;
221 cfg->lane_en[i] = true;
225 cfg->mpll_cfg = dcn2_mpll_cfg[0];
228 cfg->mpll_cfg = dcn2_mpll_cfg[1];
231 cfg->mpll_cfg = dcn2_mpll_cfg[2];
234 cfg->mpll_cfg = dcn2_mpll_cfg[3];
252 struct dpcssys_phy_seq_cfg *cfg = &enc20->phy_seq_cfg; local in function:dcn20_link_encoder_enable_dp_output
259 if (!update_cfg_data(enc10, link_settings, cfg))
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn21/
amdgpu_dcn21_link_encoder.c 178 struct dpcssys_phy_seq_cfg *cfg)
182 cfg->load_sram_fw = false;
183 cfg->use_calibration_setting = true;
187 cfg->lane_en[i] = true;
191 cfg->mpll_cfg = dcn21_mpll_cfg_ref[0];
194 cfg->mpll_cfg = dcn21_mpll_cfg_ref[1];
197 cfg->mpll_cfg = dcn21_mpll_cfg_ref[2];
200 cfg->mpll_cfg = dcn21_mpll_cfg_ref[3];
289 struct dpcssys_phy_seq_cfg *cfg = &enc21->phy_seq_cfg; local in function:dcn21_link_encoder_enable_dp_output
299 if (!update_cfg_data(enc10, link_settings, cfg))
    [all...]
amdgpu_dcn21_link_encoder.c 178 struct dpcssys_phy_seq_cfg *cfg)
182 cfg->load_sram_fw = false;
183 cfg->use_calibration_setting = true;
187 cfg->lane_en[i] = true;
191 cfg->mpll_cfg = dcn21_mpll_cfg_ref[0];
194 cfg->mpll_cfg = dcn21_mpll_cfg_ref[1];
197 cfg->mpll_cfg = dcn21_mpll_cfg_ref[2];
200 cfg->mpll_cfg = dcn21_mpll_cfg_ref[3];
289 struct dpcssys_phy_seq_cfg *cfg = &enc21->phy_seq_cfg; local in function:dcn21_link_encoder_enable_dp_output
299 if (!update_cfg_data(enc10, link_settings, cfg))
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/xen/
xen_drm_front.h 103 struct xen_drm_front_cfg cfg; member in struct:xen_drm_front_info
xen_drm_front.h 103 struct xen_drm_front_cfg cfg; member in struct:xen_drm_front_info
xen_drm_front_evtchnl.c 235 struct xen_drm_front_cfg *cfg; local in function:xen_drm_front_evtchnl_create_all
238 cfg = &front_info->cfg;
241 kcalloc(cfg->num_connectors,
249 for (conn = 0; conn < cfg->num_connectors; conn++) {
266 front_info->num_evt_pairs = cfg->num_connectors;
305 plat_data = &front_info->cfg;
  /src/sys/arch/mips/mips/
cache.c 1067 uint32_t cfg, cfg1; local in function:mips_config_cache_modern
1069 cfg = mips3_cp0_config_read();
1135 mci->mci_picache_vivt = (cfg & MIPSNN_CFG_VI) != 0;
1378 if (MIPSNN_GET(CFG_AR, cfg) == MIPSNN_CFG_AR_REV2) {
1533 mipsNN_cache_init(cfg, cfg1);
  /src/sys/arch/sandpoint/stand/altboot/
pci.c 118 unsigned cfg; local in function:pcicfgread
120 cfg = tag | (off &~ 03);
121 iohtole32(CONFIG_ADDR, cfg);
128 unsigned cfg; local in function:pcicfgwrite
130 cfg = tag | (off &~ 03);
131 iohtole32(CONFIG_ADDR, cfg);
138 unsigned cfg; local in function:cfgread
141 cfg = (1U << 31) | (b << 16) | (d << 11) | (f << 8) | off | 0;
142 iohtole32(CONFIG_ADDR, cfg);
149 unsigned cfg; local in function:cfgwrite
    [all...]
  /src/sys/dev/sbus/
cs4231_sbus.c 269 int cfg; local in function:cs4231_sbus_trigger_output
282 cfg = ad_read(&sc->sc_ad1848, SP_INTERFACE_CONFIG);
284 (cfg | PLAYBACK_ENABLE));
317 int cfg; local in function:cs4231_sbus_halt_output
347 cfg = ad_read(&sc->sc_ad1848, SP_INTERFACE_CONFIG);
348 ad_write(&sc->sc_ad1848, SP_INTERFACE_CONFIG,(cfg & ~PLAYBACK_ENABLE));
402 int cfg; local in function:cs4231_sbus_trigger_input
415 cfg = ad_read(&sc->sc_ad1848, SP_INTERFACE_CONFIG);
417 (cfg | CAPTURE_ENABLE));
448 int cfg; local in function:cs4231_sbus_halt_input
    [all...]
  /src/sys/dev/tc/
tcu.c 109 uint8_t cfg; local in function:tcu_attach
130 cfg = bus_space_read_1(iot, ioh, TCU_CFG);
141 "\0", cfg);
144 if ((cfg & TCU_CFG_S1_1) != 0 && ta->ta_busspeed != TC_SPEED_12_5_MHZ)
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dce110/
amdgpu_dce110_clk_mgr.c 135 struct dm_pp_single_disp_config *cfg = local in function:dce110_fill_display_configs
152 cfg->signal = pipe_ctx->stream->signal;
153 cfg->pipe_idx = pipe_ctx->stream_res.tg->inst;
154 cfg->src_height = stream->src.height;
155 cfg->src_width = stream->src.width;
156 cfg->ddi_channel_mapping =
158 cfg->transmitter =
160 cfg->link_settings.lane_count =
162 cfg->link_settings.link_rate =
164 cfg->link_settings.link_spread
    [all...]

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