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Searched defs:cg_sclk_dpm_ctrl_5 (Results 1 - 2 of 2) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_sumo_dpm.c	`785 WREG32_P(CG_SCLK_DPM_CTRL_5, SCLK_FSTATE_BOOTUP(0), ~SCLK_FSTATE_BOOTUP_MASK); 934 u32 cg_sclk_dpm_ctrl_5 = RREG32(CG_SCLK_DPM_CTRL_5); local in function:sumo_program_ttp 939 cg_sclk_dpm_ctrl_5 &= ~(TT_TP_MASK \| TT_TU_MASK); 940 cg_sclk_dpm_ctrl_5 \|= TT_TP(p) \| TT_TU(u); 942 WREG32(CG_SCLK_DPM_CTRL_5, cg_sclk_dpm_ctrl_5);`
radeon_sumo_dpm.c	`785 WREG32_P(CG_SCLK_DPM_CTRL_5, SCLK_FSTATE_BOOTUP(0), ~SCLK_FSTATE_BOOTUP_MASK); 934 u32 cg_sclk_dpm_ctrl_5 = RREG32(CG_SCLK_DPM_CTRL_5); local in function:sumo_program_ttp 939 cg_sclk_dpm_ctrl_5 &= ~(TT_TP_MASK \| TT_TU_MASK); 940 cg_sclk_dpm_ctrl_5 \|= TT_TP(p) \| TT_TU(u); 942 WREG32(CG_SCLK_DPM_CTRL_5, cg_sclk_dpm_ctrl_5);`

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