/src/sys/arch/arm/amlogic/ |
meson_sdhc.c | 391 uint32_t clk2; local in function:meson_sdhc_set_clock 426 clk2 = SDHC_READ(sc, SD_CLK2_REG); 427 clk2 &= ~SD_CLK2_SD_CLK_PHASE; 428 clk2 |= __SHIFTIN(1, SD_CLK2_SD_CLK_PHASE); 429 clk2 &= ~SD_CLK2_RX_CLK_PHASE; 430 clk2 |= __SHIFTIN(meson_sdhc_default_rx_phase(sc), 432 SDHC_WRITE(sc, SD_CLK2_REG, clk2);
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meson_sdhc.c | 391 uint32_t clk2; local in function:meson_sdhc_set_clock 426 clk2 = SDHC_READ(sc, SD_CLK2_REG); 427 clk2 &= ~SD_CLK2_SD_CLK_PHASE; 428 clk2 |= __SHIFTIN(1, SD_CLK2_SD_CLK_PHASE); 429 clk2 &= ~SD_CLK2_RX_CLK_PHASE; 430 clk2 |= __SHIFTIN(meson_sdhc_default_rx_phase(sc), 432 SDHC_WRITE(sc, SD_CLK2_REG, clk2);
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