| /src/sys/arch/arm/amlogic/ |
| meson_sdio.c | 158 struct clk *clk_clkin, *clk_core; local in function:meson_sdio_attach
173 clk_core = fdtbus_clock_get(phandle, "core");
174 if (clk_core == NULL || clk_enable(clk_core) != 0) {
238 aprint_normal_dev(self, "core %u Hz, clkin %u Hz\n", clk_get_rate(clk_core), clk_get_rate(clk_clkin));
|
| meson_sdio.c | 158 struct clk *clk_clkin, *clk_core; local in function:meson_sdio_attach
173 clk_core = fdtbus_clock_get(phandle, "core");
174 if (clk_core == NULL || clk_enable(clk_core) != 0) {
238 aprint_normal_dev(self, "core %u Hz, clkin %u Hz\n", clk_get_rate(clk_core), clk_get_rate(clk_clkin));
|
| meson_sdhc.c | 179 struct clk *clk_clkin, *clk_core; local in function:meson_sdhc_attach
194 clk_core = fdtbus_clock_get(phandle, "core");
195 if (clk_core == NULL) {
196 clk_core = fdtbus_clock_get(phandle, "pclk");
198 if (clk_core == NULL || clk_enable(clk_core) != 0) {
265 aprint_normal_dev(self, "core %u Hz, clkin %u Hz\n", clk_get_rate(clk_core), clk_get_rate(clk_clkin));
|
| meson_sdhc.c | 179 struct clk *clk_clkin, *clk_core; local in function:meson_sdhc_attach
194 clk_core = fdtbus_clock_get(phandle, "core");
195 if (clk_core == NULL) {
196 clk_core = fdtbus_clock_get(phandle, "pclk");
198 if (clk_core == NULL || clk_enable(clk_core) != 0) {
265 aprint_normal_dev(self, "core %u Hz, clkin %u Hz\n", clk_get_rate(clk_core), clk_get_rate(clk_clkin));
|
| /src/sys/external/gpl2/dts/dist/arch/mips/boot/dts/img/ |
| pistachio.dtsi | 29 clocks = <&clk_core CLK_MIPS_PLL>;
139 <&clk_core CLK_I2S>;
141 assigned-clocks = <&clk_core CLK_I2S_DIV>;
159 <&clk_core CLK_AUDIO_DAC>;
161 assigned-clocks = <&clk_core CLK_AUDIO_DAC_DIV>;
176 <&clk_core CLK_SPDIF>;
178 assigned-clocks = <&clk_core CLK_SPDIF_DIV>;
215 clocks = <&clk_core CLK_SPI0>, <&cr_periph SYS_CLK_SPI0_MASTER>;
230 clocks = <&clk_core CLK_SPI1>, <&cr_periph SYS_CLK_SPI1>;
257 clocks = <&clk_core CLK_UART0>, <&cr_periph SYS_CLK_UART0>
841 clk_core: clk@18144000 { label
[all...] |
| pistachio.dtsi | 29 clocks = <&clk_core CLK_MIPS_PLL>;
139 <&clk_core CLK_I2S>;
141 assigned-clocks = <&clk_core CLK_I2S_DIV>;
159 <&clk_core CLK_AUDIO_DAC>;
161 assigned-clocks = <&clk_core CLK_AUDIO_DAC_DIV>;
176 <&clk_core CLK_SPDIF>;
178 assigned-clocks = <&clk_core CLK_SPDIF_DIV>;
215 clocks = <&clk_core CLK_SPI0>, <&cr_periph SYS_CLK_SPI0_MASTER>;
230 clocks = <&clk_core CLK_SPI1>, <&cr_periph SYS_CLK_SPI1>;
257 clocks = <&clk_core CLK_UART0>, <&cr_periph SYS_CLK_UART0>
841 clk_core: clk@18144000 { label
[all...] |
