| /src/sys/arch/mips/atheros/ |
| ar9344.c | 161 uint32_t clk_ctl = GETPLLREG(ARCHIP_PLL_CPU_DDR_CLOCK_CONTROL); local in function:ar9344_get_freqs
162 post_div = __SHIFTOUT(clk_ctl,
164 if (clk_ctl & AR9344_CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL) {
170 post_div = __SHIFTOUT(clk_ctl,
172 if (clk_ctl & AR9344_CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL) {
180 post_div = __SHIFTOUT(clk_ctl,
182 if (clk_ctl & AR9344_CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL) {
|
| ar9344.c | 161 uint32_t clk_ctl = GETPLLREG(ARCHIP_PLL_CPU_DDR_CLOCK_CONTROL); local in function:ar9344_get_freqs
162 post_div = __SHIFTOUT(clk_ctl,
164 if (clk_ctl & AR9344_CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL) {
170 post_div = __SHIFTOUT(clk_ctl,
172 if (clk_ctl & AR9344_CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL) {
180 post_div = __SHIFTOUT(clk_ctl,
182 if (clk_ctl & AR9344_CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL) {
|
| /src/sys/arch/hppa/dev/ |
| elroyreg.h | 100 uint64_t clk_ctl; /* 0x618 */ member in struct:elroy_regs
|
| elroyreg.h | 100 uint64_t clk_ctl; /* 0x618 */ member in struct:elroy_regs
|
| /src/sys/dev/pci/ |
| machfb.c | 934 int clk_ctl, clock; local in function:mach64_get_mode
943 clk_ctl = regr(sc, CLOCK_CNTL);
944 clock = clk_ctl & 3;
|
| machfb.c | 934 int clk_ctl, clock; local in function:mach64_get_mode
943 clk_ctl = regr(sc, CLOCK_CNTL);
944 clock = clk_ctl & 3;
|
