| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/ |
| amdgpu_renoir_ppt.c | 230 static int renoir_get_dpm_clk_limited(struct smu_context *smu, enum smu_clk_type clk_type,
235 if (!clk_table || clk_type >= SMU_CLK_COUNT)
238 GET_DPM_CUR_FREQ(clk_table, clk_type, dpm_level, *freq);
244 enum smu_clk_type clk_type, char *buf)
251 if (!clk_table || clk_type >= SMU_CLK_COUNT)
260 switch (clk_type) {
305 GET_DPM_CUR_FREQ(clk_table, clk_type, i, value);
395 enum smu_clk_type clk_type,
405 clk_id = smu_clk_get_index(smu, clk_type);
418 enum smu_clk_type clk_type; local in function:renoir_force_dpm_limit_value
445 enum smu_clk_type clk_type; local in function:renoir_unforce_dpm_levels
448 enum smu_clk_type clk_type; member in struct:renoir_unforce_dpm_levels::clk_feature_map
[all...] |
| amdgpu_navi10_ppt.c | 716 enum smu_clk_type clk_type,
726 clk_id = smu_clk_get_index(smu, clk_type);
735 static bool navi10_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type)
741 clk_index = smu_clk_get_index(smu, clk_type);
764 enum smu_clk_type clk_type, char *buf)
782 switch (clk_type) {
790 ret = smu_get_current_clk_freq(smu, clk_type, &cur_value);
797 ret = smu_get_dpm_level_count(smu, clk_type, &count);
801 if (!navi10_is_support_fine_grained_dpm(smu, clk_type)) {
803 ret = smu_get_dpm_freq_by_index(smu, clk_type, i, &value)
1099 enum smu_clk_type clk_type; local in function:navi10_force_dpm_limit_value
1126 enum smu_clk_type clk_type; local in function:navi10_unforce_dpm_levels
[all...] |
| amdgpu_smu_v11_0.c | 1319 enum amd_pp_clock_type clk_type = clock_req->clock_type; local in function:smu_v11_0_display_clock_voltage_request
1329 switch (clk_type) {
1769 int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
1775 clk_id = smu_clk_get_index(smu, clk_type);
1804 int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
1810 clk_id = smu_clk_get_index(smu, clk_type);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/ |
| dm_services_types.h | 84 #define DC_DECODE_PP_CLOCK_TYPE(clk_type) \
85 (clk_type) == DM_PP_CLOCK_TYPE_DISPLAY_CLK ? "Display" : \
86 (clk_type) == DM_PP_CLOCK_TYPE_ENGINE_CLK ? "Engine" : \
87 (clk_type) == DM_PP_CLOCK_TYPE_MEMORY_CLK ? "Memory" : \
88 (clk_type) == DM_PP_CLOCK_TYPE_DCFCLK ? "DCF" : \
89 (clk_type) == DM_PP_CLOCK_TYPE_DCEFCLK ? "DCEF" : \
90 (clk_type) == DM_PP_CLOCK_TYPE_SOCCLK ? "SoC" : \
91 (clk_type) == DM_PP_CLOCK_TYPE_PIXELCLK ? "Pixel" : \
92 (clk_type) == DM_PP_CLOCK_TYPE_DISPLAYPHYCLK ? "Display PHY" : \
93 (clk_type) == DM_PP_CLOCK_TYPE_DPPCLK ? "DPP" :
256 enum dm_pp_clock_type clk_type; member in struct:dm_pp_clock_for_voltage_req
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/ |
| amdgpu_smu10_hwmgr.c | 67 enum amd_pp_clock_type clk_type = clock_req->clock_type; local in function:smu10_display_clock_voltage_request
71 switch (clk_type) {
|
| amdgpu_vega12_hwmgr.c | 1440 enum amd_pp_clock_type clk_type = clock_req->clock_type; local in function:vega12_display_clock_voltage_request
1446 switch (clk_type) {
|
| amdgpu_vega20_hwmgr.c | 2256 enum amd_pp_clock_type clk_type = clock_req->clock_type; local in function:vega20_display_clock_voltage_request
2262 switch (clk_type) {
|
| amdgpu_vega10_hwmgr.c | 3910 enum amd_pp_clock_type clk_type = clock_req->clock_type; local in function:vega10_display_clock_voltage_request
3915 switch (clk_type) {
|
