| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/renesas/ |
| r9a07g044.dtsi | 9 #include <dt-bindings/clock/r9a07g044-cpg.h>
92 clocks = <&cpg CPG_MOD R9A07G044_SCIF0_CLK_PCK>;
94 power-domains = <&cpg>;
95 resets = <&cpg R9A07G044_SCIF0_RST_SYSTEM_N>;
113 clocks = <&cpg CPG_MOD R9A07G044_CANFD_PCLK>,
114 <&cpg CPG_CORE R9A07G044_CLK_P0_DIV2>,
117 assigned-clocks = <&cpg CPG_CORE R9A07G044_CLK_P0_DIV2>;
119 resets = <&cpg R9A07G044_CANFD_RSTP_N>,
120 <&cpg R9A07G044_CANFD_RSTC_N>;
122 power-domains = <&cpg>;
263 cpg: clock-controller@11010000 { label
[all...] |
| r9a07g044.dtsi | 9 #include <dt-bindings/clock/r9a07g044-cpg.h>
92 clocks = <&cpg CPG_MOD R9A07G044_SCIF0_CLK_PCK>;
94 power-domains = <&cpg>;
95 resets = <&cpg R9A07G044_SCIF0_RST_SYSTEM_N>;
113 clocks = <&cpg CPG_MOD R9A07G044_CANFD_PCLK>,
114 <&cpg CPG_CORE R9A07G044_CLK_P0_DIV2>,
117 assigned-clocks = <&cpg CPG_CORE R9A07G044_CLK_P0_DIV2>;
119 resets = <&cpg R9A07G044_CANFD_RSTP_N>,
120 <&cpg R9A07G044_CANFD_RSTC_N>;
122 power-domains = <&cpg>;
263 cpg: clock-controller@11010000 { label
[all...] |
| r9a07g044.dtsi | 9 #include <dt-bindings/clock/r9a07g044-cpg.h>
92 clocks = <&cpg CPG_MOD R9A07G044_SCIF0_CLK_PCK>;
94 power-domains = <&cpg>;
95 resets = <&cpg R9A07G044_SCIF0_RST_SYSTEM_N>;
113 clocks = <&cpg CPG_MOD R9A07G044_CANFD_PCLK>,
114 <&cpg CPG_CORE R9A07G044_CLK_P0_DIV2>,
117 assigned-clocks = <&cpg CPG_CORE R9A07G044_CLK_P0_DIV2>;
119 resets = <&cpg R9A07G044_CANFD_RSTP_N>,
120 <&cpg R9A07G044_CANFD_RSTC_N>;
122 power-domains = <&cpg>;
263 cpg: clock-controller@11010000 { label
[all...] |
| r9a07g043.dtsi | 8 #include <dt-bindings/clock/r9a07g043-cpg.h>
140 clocks = <&cpg CPG_MOD R9A07G043_MTU_X_MCK_MTU3>;
141 power-domains = <&cpg>;
142 resets = <&cpg R9A07G043_MTU_X_PRESET_MTU3>;
155 clocks = <&cpg CPG_MOD R9A07G043_SSI0_PCLK2>,
156 <&cpg CPG_MOD R9A07G043_SSI0_PCLK_SFR>,
159 resets = <&cpg R9A07G043_SSI0_RST_M2_REG>;
162 power-domains = <&cpg>;
175 clocks = <&cpg CPG_MOD R9A07G043_SSI1_PCLK2>,
176 <&cpg CPG_MOD R9A07G043_SSI1_PCLK_SFR>
577 cpg: clock-controller@11010000 { label
[all...] |
| r9a07g043.dtsi | 8 #include <dt-bindings/clock/r9a07g043-cpg.h>
140 clocks = <&cpg CPG_MOD R9A07G043_MTU_X_MCK_MTU3>;
141 power-domains = <&cpg>;
142 resets = <&cpg R9A07G043_MTU_X_PRESET_MTU3>;
155 clocks = <&cpg CPG_MOD R9A07G043_SSI0_PCLK2>,
156 <&cpg CPG_MOD R9A07G043_SSI0_PCLK_SFR>,
159 resets = <&cpg R9A07G043_SSI0_RST_M2_REG>;
162 power-domains = <&cpg>;
175 clocks = <&cpg CPG_MOD R9A07G043_SSI1_PCLK2>,
176 <&cpg CPG_MOD R9A07G043_SSI1_PCLK_SFR>
577 cpg: clock-controller@11010000 { label
[all...] |
| r9a07g043.dtsi | 8 #include <dt-bindings/clock/r9a07g043-cpg.h>
140 clocks = <&cpg CPG_MOD R9A07G043_MTU_X_MCK_MTU3>;
141 power-domains = <&cpg>;
142 resets = <&cpg R9A07G043_MTU_X_PRESET_MTU3>;
155 clocks = <&cpg CPG_MOD R9A07G043_SSI0_PCLK2>,
156 <&cpg CPG_MOD R9A07G043_SSI0_PCLK_SFR>,
159 resets = <&cpg R9A07G043_SSI0_RST_M2_REG>;
162 power-domains = <&cpg>;
175 clocks = <&cpg CPG_MOD R9A07G043_SSI1_PCLK2>,
176 <&cpg CPG_MOD R9A07G043_SSI1_PCLK_SFR>
577 cpg: clock-controller@11010000 { label
[all...] |
| /src/usr.sbin/makefs/ |
| ffs.h | 48 int cpg; /* cylinders per group */ member in struct:__anon6ccfc86b0108
49 int cpgflg; /* cpg was specified by user */
|
| ffs.h | 48 int cpg; /* cylinders per group */ member in struct:__anon6ccfc86b0108
49 int cpgflg; /* cpg was specified by user */
|
| ffs.h | 48 int cpg; /* cylinders per group */ member in struct:__anon6ccfc86b0108
49 int cpgflg; /* cpg was specified by user */
|
| /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/ |
| r7s9210.dtsi | 10 #include <dt-bindings/clock/r7s9210-cpg-mssr.h>
82 clocks = <&cpg CPG_MOD 47>;
84 power-domains = <&cpg>;
99 clocks = <&cpg CPG_MOD 46>;
101 power-domains = <&cpg>;
116 clocks = <&cpg CPG_MOD 45>;
118 power-domains = <&cpg>;
133 clocks = <&cpg CPG_MOD 44>;
135 power-domains = <&cpg>;
150 clocks = <&cpg CPG_MOD 43>
460 cpg: clock-controller@fcfe0010 { label
[all...] |
| r7s9210.dtsi | 10 #include <dt-bindings/clock/r7s9210-cpg-mssr.h>
82 clocks = <&cpg CPG_MOD 47>;
84 power-domains = <&cpg>;
99 clocks = <&cpg CPG_MOD 46>;
101 power-domains = <&cpg>;
116 clocks = <&cpg CPG_MOD 45>;
118 power-domains = <&cpg>;
133 clocks = <&cpg CPG_MOD 44>;
135 power-domains = <&cpg>;
150 clocks = <&cpg CPG_MOD 43>
460 cpg: clock-controller@fcfe0010 { label
[all...] |
| r7s9210.dtsi | 10 #include <dt-bindings/clock/r7s9210-cpg-mssr.h>
82 clocks = <&cpg CPG_MOD 47>;
84 power-domains = <&cpg>;
99 clocks = <&cpg CPG_MOD 46>;
101 power-domains = <&cpg>;
116 clocks = <&cpg CPG_MOD 45>;
118 power-domains = <&cpg>;
133 clocks = <&cpg CPG_MOD 44>;
135 power-domains = <&cpg>;
150 clocks = <&cpg CPG_MOD 43>
460 cpg: clock-controller@fcfe0010 { label
[all...] |
| r8a7792.dtsi | 8 #include <dt-bindings/clock/r8a7792-cpg-mssr.h>
54 clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
65 clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
114 clocks = <&cpg CPG_MOD 402>;
116 resets = <&cpg 402>;
130 clocks = <&cpg CPG_MOD 912>;
132 resets = <&cpg 912>;
145 clocks = <&cpg CPG_MOD 911>;
147 resets = <&cpg 911>;
160 clocks = <&cpg CPG_MOD 910>
305 cpg: clock-controller@e6150000 { label
[all...] |
| r8a7792.dtsi | 8 #include <dt-bindings/clock/r8a7792-cpg-mssr.h>
54 clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
65 clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
114 clocks = <&cpg CPG_MOD 402>;
116 resets = <&cpg 402>;
130 clocks = <&cpg CPG_MOD 912>;
132 resets = <&cpg 912>;
145 clocks = <&cpg CPG_MOD 911>;
147 resets = <&cpg 911>;
160 clocks = <&cpg CPG_MOD 910>
305 cpg: clock-controller@e6150000 { label
[all...] |
| r8a7792.dtsi | 8 #include <dt-bindings/clock/r8a7792-cpg-mssr.h>
54 clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
65 clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
114 clocks = <&cpg CPG_MOD 402>;
116 resets = <&cpg 402>;
130 clocks = <&cpg CPG_MOD 912>;
132 resets = <&cpg 912>;
145 clocks = <&cpg CPG_MOD 911>;
147 resets = <&cpg 911>;
160 clocks = <&cpg CPG_MOD 910>
305 cpg: clock-controller@e6150000 { label
[all...] |
| r8a77470.dtsi | 10 #include <dt-bindings/clock/r8a77470-cpg-mssr.h>
34 clocks = <&cpg CPG_CORE R8A77470_CLK_Z2>;
45 clocks = <&cpg CPG_CORE R8A77470_CLK_Z2>;
94 clocks = <&cpg CPG_MOD 402>;
96 resets = <&cpg 402>;
110 clocks = <&cpg CPG_MOD 912>;
112 resets = <&cpg 912>;
125 clocks = <&cpg CPG_MOD 911>;
127 resets = <&cpg 911>;
140 clocks = <&cpg CPG_MOD 910>
196 cpg: clock-controller@e6150000 { label
[all...] |
| /src/lib/libukfs/ |
| ukfs_int_disklabel.h | 146 uint16_t cpg; /* UFS: FS cylinders per group */ member in union:ukfs__disklabel::ukfs__partition::__anone7ac4155040a
149 #define p_cpg __partition_u1.cpg
|
| ukfs_int_disklabel.h | 146 uint16_t cpg; /* UFS: FS cylinders per group */ member in union:ukfs__disklabel::ukfs__partition::__anone7ac4155040a
149 #define p_cpg __partition_u1.cpg
|
| ukfs_int_disklabel.h | 146 uint16_t cpg; /* UFS: FS cylinders per group */ member in union:ukfs__disklabel::ukfs__partition::__anone7ac4155040a
149 #define p_cpg __partition_u1.cpg
|
| /src/sys/arch/atari/stand/tostools/aptck/ |
| disklbl.h | 128 u_int16_t cpg; /* UFS: FS cylinders per group */ member in union:disklabel::partition::__anonb2fa26a4030a
131 #define p_cpg __partition_u1.cpg
|
| disklbl.h | 128 u_int16_t cpg; /* UFS: FS cylinders per group */ member in union:disklabel::partition::__anonb2fa26a4030a
131 #define p_cpg __partition_u1.cpg
|
| disklbl.h | 128 u_int16_t cpg; /* UFS: FS cylinders per group */ member in union:disklabel::partition::__anonb2fa26a4030a
131 #define p_cpg __partition_u1.cpg
|
| /src/sys/arch/atari/stand/tostools/libtos/ |
| disklbl.h | 128 u_int16_t cpg; /* UFS: FS cylinders per group */ member in union:disklabel::partition::__anon7bc9703e030a
131 #define p_cpg __partition_u1.cpg
|
| disklbl.h | 128 u_int16_t cpg; /* UFS: FS cylinders per group */ member in union:disklabel::partition::__anon7bc9703e030a
131 #define p_cpg __partition_u1.cpg
|
| disklbl.h | 128 u_int16_t cpg; /* UFS: FS cylinders per group */ member in union:disklabel::partition::__anon7bc9703e030a
131 #define p_cpg __partition_u1.cpg
|
