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Searched defs:cr_periph (Results 1 - 6 of 6) sorted by relevancy

/src/sys/external/gpl2/dts/dist/arch/mips/boot/dts/img/
pistachio.dtsi	`49 <&cr_periph SYS_CLK_I2C0>; 67 <&cr_periph SYS_CLK_I2C1>; 85 <&cr_periph SYS_CLK_I2C2>; 103 <&cr_periph SYS_CLK_I2C3>; 122 clocks = <&cr_periph SYS_CLK_I2S_IN>; 138 clocks = <&cr_periph SYS_CLK_I2S_OUT>, 158 clocks = <&cr_periph SYS_CLK_PAUD_OUT>, 175 clocks = <&cr_periph SYS_CLK_SPDIF_OUT>, 194 clocks = <&cr_periph SYS_CLK_SPDIF_IN>; 215 clocks = <&clk_core CLK_SPI0>, <&cr_periph SYS_CLK_SPI0_MASTER> 859 cr_periph: clk@18148000 { label [all...]`
pistachio.dtsi	`49 <&cr_periph SYS_CLK_I2C0>; 67 <&cr_periph SYS_CLK_I2C1>; 85 <&cr_periph SYS_CLK_I2C2>; 103 <&cr_periph SYS_CLK_I2C3>; 122 clocks = <&cr_periph SYS_CLK_I2S_IN>; 138 clocks = <&cr_periph SYS_CLK_I2S_OUT>, 158 clocks = <&cr_periph SYS_CLK_PAUD_OUT>, 175 clocks = <&cr_periph SYS_CLK_SPDIF_OUT>, 194 clocks = <&cr_periph SYS_CLK_SPDIF_IN>; 215 clocks = <&clk_core CLK_SPI0>, <&cr_periph SYS_CLK_SPI0_MASTER> 859 cr_periph: clk@18148000 { label [all...]`
pistachio.dtsi	`49 <&cr_periph SYS_CLK_I2C0>; 67 <&cr_periph SYS_CLK_I2C1>; 85 <&cr_periph SYS_CLK_I2C2>; 103 <&cr_periph SYS_CLK_I2C3>; 122 clocks = <&cr_periph SYS_CLK_I2S_IN>; 138 clocks = <&cr_periph SYS_CLK_I2S_OUT>, 158 clocks = <&cr_periph SYS_CLK_PAUD_OUT>, 175 clocks = <&cr_periph SYS_CLK_SPDIF_OUT>, 194 clocks = <&cr_periph SYS_CLK_SPDIF_IN>; 215 clocks = <&clk_core CLK_SPI0>, <&cr_periph SYS_CLK_SPI0_MASTER> 859 cr_periph: clk@18148000 { label [all...]`
pistachio.dtsi	`49 <&cr_periph SYS_CLK_I2C0>; 67 <&cr_periph SYS_CLK_I2C1>; 85 <&cr_periph SYS_CLK_I2C2>; 103 <&cr_periph SYS_CLK_I2C3>; 122 clocks = <&cr_periph SYS_CLK_I2S_IN>; 138 clocks = <&cr_periph SYS_CLK_I2S_OUT>, 158 clocks = <&cr_periph SYS_CLK_PAUD_OUT>, 175 clocks = <&cr_periph SYS_CLK_SPDIF_OUT>, 194 clocks = <&cr_periph SYS_CLK_SPDIF_IN>; 215 clocks = <&clk_core CLK_SPI0>, <&cr_periph SYS_CLK_SPI0_MASTER> 859 cr_periph: clk@18148000 { label [all...]`
pistachio.dtsi	`49 <&cr_periph SYS_CLK_I2C0>; 67 <&cr_periph SYS_CLK_I2C1>; 85 <&cr_periph SYS_CLK_I2C2>; 103 <&cr_periph SYS_CLK_I2C3>; 122 clocks = <&cr_periph SYS_CLK_I2S_IN>; 138 clocks = <&cr_periph SYS_CLK_I2S_OUT>, 158 clocks = <&cr_periph SYS_CLK_PAUD_OUT>, 175 clocks = <&cr_periph SYS_CLK_SPDIF_OUT>, 194 clocks = <&cr_periph SYS_CLK_SPDIF_IN>; 215 clocks = <&clk_core CLK_SPI0>, <&cr_periph SYS_CLK_SPI0_MASTER> 859 cr_periph: clk@18148000 { label [all...]`
pistachio.dtsi	`49 <&cr_periph SYS_CLK_I2C0>; 67 <&cr_periph SYS_CLK_I2C1>; 85 <&cr_periph SYS_CLK_I2C2>; 103 <&cr_periph SYS_CLK_I2C3>; 122 clocks = <&cr_periph SYS_CLK_I2S_IN>; 138 clocks = <&cr_periph SYS_CLK_I2S_OUT>, 158 clocks = <&cr_periph SYS_CLK_PAUD_OUT>, 175 clocks = <&cr_periph SYS_CLK_SPDIF_OUT>, 194 clocks = <&cr_periph SYS_CLK_SPDIF_IN>; 215 clocks = <&clk_core CLK_SPI0>, <&cr_periph SYS_CLK_SPI0_MASTER> 859 cr_periph: clk@18148000 { label [all...]`

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