| /src/sys/arch/x68k/dev/ |
| grf_gv.c | 138 volatile struct crtc *crtc = &IODEVbase->io_crtc; local in function:gv_mode
139 /* Reset CRTC, set dwidth and dheight accordingly */
140 crtc->r20 = (crtc->r20 & 0xFF00) | 0x1a;
141 crtc->r08 = 0x1b;
142 crtc->r07 = 0x19c;
143 crtc->r06 = 0x1c;
144 crtc->r05 = 0x02;
145 crtc->r04 = 0x019f
[all...] |
| grf_tv.c | 138 volatile struct crtc *crtc = &IODEVbase->io_crtc; local in function:cc_mode
139 /* Reset CRTC, set dwidth and dheight accordingly */
140 crtc->r20 = (crtc->r20 & 0xFF00) | 0x1a;
141 crtc->r08 = 0x1b;
142 crtc->r07 = 0x19c;
143 crtc->r06 = 0x1c;
144 crtc->r05 = 0x02;
145 crtc->r04 = 0x019f
[all...] |
| grf_gv.c | 138 volatile struct crtc *crtc = &IODEVbase->io_crtc; local in function:gv_mode
139 /* Reset CRTC, set dwidth and dheight accordingly */
140 crtc->r20 = (crtc->r20 & 0xFF00) | 0x1a;
141 crtc->r08 = 0x1b;
142 crtc->r07 = 0x19c;
143 crtc->r06 = 0x1c;
144 crtc->r05 = 0x02;
145 crtc->r04 = 0x019f
[all...] |
| grf_tv.c | 138 volatile struct crtc *crtc = &IODEVbase->io_crtc; local in function:cc_mode
139 /* Reset CRTC, set dwidth and dheight accordingly */
140 crtc->r20 = (crtc->r20 & 0xFF00) | 0x1a;
141 crtc->r08 = 0x1b;
142 crtc->r07 = 0x19c;
143 crtc->r06 = 0x1c;
144 crtc->r05 = 0x02;
145 crtc->r04 = 0x019f
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce80/ |
| amdgpu_dce80_hw_sequencer.c | 45 uint32_t crtc; member in struct:dce80_hw_seq_reg_offsets
50 .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
53 .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
56 .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
59 .crtc = (mmCRTC3_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
62 .crtc = (mmCRTC4_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
65 .crtc = (mmCRTC5_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
70 (reg + reg_offsets[id].crtc)
|
| amdgpu_dce80_hw_sequencer.c | 45 uint32_t crtc; member in struct:dce80_hw_seq_reg_offsets
50 .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
53 .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
56 .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
59 .crtc = (mmCRTC3_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
62 .crtc = (mmCRTC4_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
65 .crtc = (mmCRTC5_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
70 (reg + reg_offsets[id].crtc)
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/dispnv04/ |
| nouveau_dispnv04_cursor.c | 36 crtc_wr_cio_state(struct drm_crtc *crtc, struct nv04_crtc_reg *crtcstate, int index)
38 NVWriteVgaCrtc(crtc->dev, nouveau_crtc(crtc)->index, index,
39 crtcstate->CRTC[index]);
48 struct drm_crtc *crtc = &nv_crtc->base; local in function:nv04_cursor_set_offset
50 regp->CRTC[NV_CIO_CRE_HCUR_ADDR0_INDEX] =
53 regp->CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX] =
55 if (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)
56 regp->CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX] |=
58 regp->CRTC[NV_CIO_CRE_HCUR_ADDR2_INDEX] = offset >> 24
[all...] |
| nouveau_dispnv04_cursor.c | 36 crtc_wr_cio_state(struct drm_crtc *crtc, struct nv04_crtc_reg *crtcstate, int index)
38 NVWriteVgaCrtc(crtc->dev, nouveau_crtc(crtc)->index, index,
39 crtcstate->CRTC[index]);
48 struct drm_crtc *crtc = &nv_crtc->base; local in function:nv04_cursor_set_offset
50 regp->CRTC[NV_CIO_CRE_HCUR_ADDR0_INDEX] =
53 regp->CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX] =
55 if (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)
56 regp->CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX] |=
58 regp->CRTC[NV_CIO_CRE_HCUR_ADDR2_INDEX] = offset >> 24
[all...] |
| nouveau_dispnv04_disp.c | 45 struct drm_crtc *crtc; local in function:nv04_display_fini
59 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
62 nouveau_fb = nouveau_framebuffer(crtc->primary->fb);
69 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
70 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
85 struct drm_crtc *crtc; local in function:nv04_display_init
96 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
97 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
111 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
114 nouveau_fb = nouveau_framebuffer(crtc->primary->fb)
201 struct nouveau_crtc *crtc; local in function:nv04_display_create
[all...] |
| nouveau_dispnv04_disp.c | 45 struct drm_crtc *crtc; local in function:nv04_display_fini
59 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
62 nouveau_fb = nouveau_framebuffer(crtc->primary->fb);
69 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
70 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
85 struct drm_crtc *crtc; local in function:nv04_display_init
96 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
97 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
111 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
114 nouveau_fb = nouveau_framebuffer(crtc->primary->fb)
201 struct nouveau_crtc *crtc; local in function:nv04_display_create
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce100/ |
| amdgpu_dce100_hw_sequencer.c | 45 uint32_t crtc; member in struct:dce100_hw_seq_reg_offsets
50 .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
53 .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
56 .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
59 .crtc = (mmCRTC3_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
62 .crtc = (mmCRTC4_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
65 .crtc = (mmCRTC5_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
70 (reg + reg_offsets[id].crtc)
|
| amdgpu_dce100_hw_sequencer.c | 45 uint32_t crtc; member in struct:dce100_hw_seq_reg_offsets
50 .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
53 .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
56 .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
59 .crtc = (mmCRTC3_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
62 .crtc = (mmCRTC4_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
65 .crtc = (mmCRTC5_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
70 (reg + reg_offsets[id].crtc)
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce112/ |
| amdgpu_dce112_hw_sequencer.c | 43 uint32_t crtc; member in struct:dce112_hw_seq_reg_offsets
49 .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
52 .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
55 .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
58 .crtc = (mmCRTC3_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
61 .crtc = (mmCRTC4_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
64 .crtc = (mmCRTC5_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
68 (reg + reg_offsets[id].crtc)
|
| amdgpu_dce112_hw_sequencer.c | 43 uint32_t crtc; member in struct:dce112_hw_seq_reg_offsets
49 .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
52 .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
55 .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
58 .crtc = (mmCRTC3_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
61 .crtc = (mmCRTC4_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
64 .crtc = (mmCRTC5_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
68 (reg + reg_offsets[id].crtc)
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce120/ |
| amdgpu_dce120_hw_sequencer.c | 55 uint32_t crtc; member in struct:dce120_hw_seq_reg_offsets
60 .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC0_CRTC_GSL_CONTROL),
63 .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC0_CRTC_GSL_CONTROL),
66 .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC0_CRTC_GSL_CONTROL),
69 .crtc = (mmCRTC3_CRTC_GSL_CONTROL - mmCRTC0_CRTC_GSL_CONTROL),
72 .crtc = (mmCRTC4_CRTC_GSL_CONTROL - mmCRTC0_CRTC_GSL_CONTROL),
75 .crtc = (mmCRTC5_CRTC_GSL_CONTROL - mmCRTC0_CRTC_GSL_CONTROL),
80 (reg + reg_offsets[id].crtc)
|
| amdgpu_dce120_hw_sequencer.c | 55 uint32_t crtc; member in struct:dce120_hw_seq_reg_offsets
60 .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC0_CRTC_GSL_CONTROL),
63 .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC0_CRTC_GSL_CONTROL),
66 .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC0_CRTC_GSL_CONTROL),
69 .crtc = (mmCRTC3_CRTC_GSL_CONTROL - mmCRTC0_CRTC_GSL_CONTROL),
72 .crtc = (mmCRTC4_CRTC_GSL_CONTROL - mmCRTC0_CRTC_GSL_CONTROL),
75 .crtc = (mmCRTC5_CRTC_GSL_CONTROL - mmCRTC0_CRTC_GSL_CONTROL),
80 (reg + reg_offsets[id].crtc)
|
| /src/sys/external/bsd/drm2/dist/drm/ |
| drm_encoder.c | 40 * Encoders represent the connecting element between the CRTC (as the overall
43 * pixel data from a CRTC and converts it to a format suitable for any attached
45 * userspace to infer cloning and connector/CRTC restrictions. Unfortunately
52 * userspace directly connects a connector with a CRTC), drivers are therefore
209 return connector->state->crtc;
217 return encoder->crtc;
225 struct drm_crtc *crtc; local in function:drm_mode_getencoder
235 crtc = drm_encoder_get_crtc(encoder);
236 if (crtc && drm_lease_held(file_priv, crtc->base.id)
[all...] |
| drm_encoder.c | 40 * Encoders represent the connecting element between the CRTC (as the overall
43 * pixel data from a CRTC and converts it to a format suitable for any attached
45 * userspace to infer cloning and connector/CRTC restrictions. Unfortunately
52 * userspace directly connects a connector with a CRTC), drivers are therefore
209 return connector->state->crtc;
217 return encoder->crtc;
225 struct drm_crtc *crtc; local in function:drm_mode_getencoder
235 crtc = drm_encoder_get_crtc(encoder);
236 if (crtc && drm_lease_held(file_priv, crtc->base.id)
[all...] |
| drm_modeset_lock.c | 180 struct drm_crtc *crtc; local in function:drm_warn_on_modeset_not_all_locked
186 drm_for_each_crtc(crtc, dev)
187 WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
404 struct drm_crtc *crtc; local in function:drm_modeset_lock_all_ctx
412 drm_for_each_crtc(crtc, dev) {
413 ret = drm_modeset_lock(&crtc->mutex, ctx);
|
| drm_self_refresh_helper.c | 41 * Once a crtc has enabled SR using &drm_self_refresh_helper_init, the
44 * on/off request with &drm_crtc_state.self_refresh_active set in crtc state
47 * During SR, drivers may choose to fully disable their crtc/encoder/bridge
53 * pipe that is in SR mode. If a crtc is driving multiple connectors, all
56 * If the crtc and connector are SR aware, but the panel connected does not
66 struct drm_crtc *crtc; member in struct:drm_self_refresh_data
79 struct drm_crtc *crtc = sr_data->crtc; local in function:drm_self_refresh_helper_entry_work
80 struct drm_device *dev = crtc->dev;
99 crtc_state = drm_atomic_get_crtc_state(state, crtc);
156 struct drm_crtc *crtc; local in function:drm_self_refresh_helper_update_avg_times
196 struct drm_crtc *crtc; local in function:drm_self_refresh_helper_alter_state
[all...] |
| drm_modeset_lock.c | 180 struct drm_crtc *crtc; local in function:drm_warn_on_modeset_not_all_locked
186 drm_for_each_crtc(crtc, dev)
187 WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
404 struct drm_crtc *crtc; local in function:drm_modeset_lock_all_ctx
412 drm_for_each_crtc(crtc, dev) {
413 ret = drm_modeset_lock(&crtc->mutex, ctx);
|
| drm_self_refresh_helper.c | 41 * Once a crtc has enabled SR using &drm_self_refresh_helper_init, the
44 * on/off request with &drm_crtc_state.self_refresh_active set in crtc state
47 * During SR, drivers may choose to fully disable their crtc/encoder/bridge
53 * pipe that is in SR mode. If a crtc is driving multiple connectors, all
56 * If the crtc and connector are SR aware, but the panel connected does not
66 struct drm_crtc *crtc; member in struct:drm_self_refresh_data
79 struct drm_crtc *crtc = sr_data->crtc; local in function:drm_self_refresh_helper_entry_work
80 struct drm_device *dev = crtc->dev;
99 crtc_state = drm_atomic_get_crtc_state(state, crtc);
156 struct drm_crtc *crtc; local in function:drm_self_refresh_helper_update_avg_times
196 struct drm_crtc *crtc; local in function:drm_self_refresh_helper_alter_state
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/i915/display/ |
| intel_dsb.c | 46 struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb); local in function:is_dsb_busy
47 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
48 enum pipe pipe = crtc->pipe;
55 struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb); local in function:intel_dsb_enable_engine
56 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
57 enum pipe pipe = crtc->pipe;
75 struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb) local in function:intel_dsb_disable_engine
169 struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb); local in function:intel_dsb_put
202 struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb); local in function:intel_dsb_indexed_reg_write
277 struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb); local in function:intel_dsb_reg_write
307 struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb); local in function:intel_dsb_commit
[all...] |
| intel_dsb.c | 46 struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb); local in function:is_dsb_busy
47 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
48 enum pipe pipe = crtc->pipe;
55 struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb); local in function:intel_dsb_enable_engine
56 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
57 enum pipe pipe = crtc->pipe;
75 struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb) local in function:intel_dsb_disable_engine
169 struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb); local in function:intel_dsb_put
202 struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb); local in function:intel_dsb_indexed_reg_write
277 struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb); local in function:intel_dsb_reg_write
307 struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb); local in function:intel_dsb_commit
[all...] |
| /src/sys/external/bsd/drm2/dist/include/drm/ |
| drm_encoder.h | 142 * @possible_crtcs: Bitmask of potential CRTC bindings, using
149 * Note that since CRTC objects can't be hotplugged the assigned indices
172 * @crtc: Currently bound CRTC, only really meaningful for non-atomic
174 * &drm_connector_state.crtc.
176 struct drm_crtc *crtc; member in struct:drm_encoder
220 * drm_encoder_crtc_ok - can a given crtc drive a given encoder?
222 * @crtc: crtc to test
224 * Returns false if @encoder can't be driven by @crtc, true otherwise
[all...] |
