| /src/sys/arch/x68k/usr.bin/tvctrl/ |
| tvctrl.c | 19 unsigned char ctl; local in function:main
31 ctl = num;
32 if (ioctl(0, ITETVCTRL, &ctl))
|
| tvctrl.c | 19 unsigned char ctl; local in function:main
31 ctl = num;
32 if (ioctl(0, ITETVCTRL, &ctl))
|
| /src/sys/modules/examples/executor/ |
| executor.c | 54 static once_t ctl; variable in typeref:typename:once_t
55 static ONCE_DECL(ctl);
77 RUN_ONCE(&ctl, runonce_example);
|
| executor.c | 54 static once_t ctl; variable in typeref:typename:once_t
55 static ONCE_DECL(ctl);
77 RUN_ONCE(&ctl, runonce_example);
|
| /src/sys/arch/mips/alchemy/ |
| au_timer.c | 75 uint32_t ctl, ctr, octr; local in function:au_cal_timers
79 ctl = bus_space_read_4(st, sh, PC_COUNTER_CONTROL);
80 if ((ctl & (CC_EO | CC_EN1)) != (CC_EO | CC_EN1))
81 SET_PC_REG(PC_COUNTER_CONTROL, 0, ctl | CC_EO | CC_EN1);
109 if ((ctl & (CC_EO | CC_EN1)) != (CC_EO | CC_EN1))
110 SET_PC_REG(PC_COUNTER_CONTROL, 0, ctl);
|
| au_timer.c | 75 uint32_t ctl, ctr, octr; local in function:au_cal_timers
79 ctl = bus_space_read_4(st, sh, PC_COUNTER_CONTROL);
80 if ((ctl & (CC_EO | CC_EN1)) != (CC_EO | CC_EN1))
81 SET_PC_REG(PC_COUNTER_CONTROL, 0, ctl | CC_EO | CC_EN1);
109 if ((ctl & (CC_EO | CC_EN1)) != (CC_EO | CC_EN1))
110 SET_PC_REG(PC_COUNTER_CONTROL, 0, ctl);
|
| /src/sys/arch/mips/include/ |
| sysarch.h | 46 int ctl; member in struct:mips_cachectl_args
|
| sysarch.h | 46 int ctl; member in struct:mips_cachectl_args
|
| netbsd32_machdep.h | 81 int ctl; member in struct:mips_cachectl_args32
|
| netbsd32_machdep.h | 81 int ctl; member in struct:mips_cachectl_args32
|
| /src/sys/arch/mvme68k/stand/sboot/ |
| console.c | 38 volatile u_char ctl; member in struct:zs_hw
55 zs->ctl = 1; rr1 = zs->ctl;
56 zs->ctl = 0;
57 if ((rr1 & 0x1) == 1 && (zs->ctl & 0x4) == 4)
60 zs->ctl = 9;
61 zs->ctl = 0x00; /* clear interrupt */
62 zs->ctl = 4;
63 zs->ctl = 0x44; /* 16x clk, 1 stop bit */
64 zs->ctl = 5
[all...] |
| console.c | 38 volatile u_char ctl; member in struct:zs_hw
55 zs->ctl = 1; rr1 = zs->ctl;
56 zs->ctl = 0;
57 if ((rr1 & 0x1) == 1 && (zs->ctl & 0x4) == 4)
60 zs->ctl = 9;
61 zs->ctl = 0x00; /* clear interrupt */
62 zs->ctl = 4;
63 zs->ctl = 0x44; /* 16x clk, 1 stop bit */
64 zs->ctl = 5
[all...] |
| /src/sys/arch/newsmips/apbus/ |
| apbus_subr.c | 74 struct apbus_ctl *ctl; local in function:apbus_device_to_hwaddr
79 ctl = apbus_dev->apbd_ctl;
80 if (ctl == NULL)
83 return (void *)ctl->apbc_hwbase;
143 printf("ctl: 0x%08x\n", (unsigned int)apdev->apbd_ctl);
|
| apbus_subr.c | 74 struct apbus_ctl *ctl; local in function:apbus_device_to_hwaddr
79 ctl = apbus_dev->apbd_ctl;
80 if (ctl == NULL)
83 return (void *)ctl->apbc_hwbase;
143 printf("ctl: 0x%08x\n", (unsigned int)apdev->apbd_ctl);
|
| /src/sys/dev/ic/ |
| rng200.c | 53 uint32_t ctl, rng, rbg; local in function:rng200_reset
56 ctl = READ4(sc, RNG200_CONTROL);
57 ctl &= ~RNG200_RBG_MASK;
58 WRITE4(sc, RNG200_CONTROL, ctl);
72 WRITE4(sc, RNG200_CONTROL, ctl | RNG200_RBG_ENABLE);
|
| rng200.c | 53 uint32_t ctl, rng, rbg; local in function:rng200_reset
56 ctl = READ4(sc, RNG200_CONTROL);
57 ctl &= ~RNG200_RBG_MASK;
58 WRITE4(sc, RNG200_CONTROL, ctl);
72 WRITE4(sc, RNG200_CONTROL, ctl | RNG200_RBG_ENABLE);
|
| /src/sys/external/bsd/drm2/dist/drm/ |
| drm_irq.c | 263 struct drm_control *ctl = data; local in function:drm_legacy_irq_control
278 switch (ctl->func) {
281 irq = ctl->irq;
287 ctl->irq != irq)
|
| drm_irq.c | 263 struct drm_control *ctl = data; local in function:drm_legacy_irq_control
278 switch (ctl->func) {
281 irq = ctl->irq;
287 ctl->irq != irq)
|
| /src/sbin/mount_portal/ |
| activate.c | 112 void *ctl = NULL; local in function:send_reply
138 ctl = malloc(cmsgsize);
139 if (ctl == NULL) {
143 memset(ctl, 0, cmsgsize);
145 cmsg = (struct cmsghdr *) ctl;
153 msg.msg_control = ctl;
176 if (ctl != NULL)
177 free(ctl);
|
| activate.c | 112 void *ctl = NULL; local in function:send_reply
138 ctl = malloc(cmsgsize);
139 if (ctl == NULL) {
143 memset(ctl, 0, cmsgsize);
145 cmsg = (struct cmsghdr *) ctl;
153 msg.msg_control = ctl;
176 if (ctl != NULL)
177 free(ctl);
|
| /src/sys/arch/alpha/pci/ |
| dwlpx.c | 80 uint32_t ctl; local in function:dwlpxmatch
91 if (badaddr(KV(PCIA_CTL(1) + ls), sizeof (ctl)) != 0) {
184 uint32_t ctl; local in function:dwlpx_init
199 sizeof (ctl)) != 0) {
225 ctl = REGVAL(PCIA_PRESENT + ccp->cc_sysbase);
234 } else if ((ctl >> PCIA_PRESENT_REVSHIFT) & PCIA_PRESENT_REVMASK) {
266 ctl = REGVAL(PCIA_CTL(i) + ccp->cc_sysbase);
267 ctl &= 0x0fffffff;
268 ctl &= ~(PCIA_CTL_MHAE(0x1f) | PCIA_CTL_IHAE(0x1f));
273 ctl |= PCIA_CTL_RMMENA | PCIA_CTL_RMMARB
[all...] |
| mcpcia.c | 132 uint32_t ctl; local in function:mcpciaattach
163 ctl = REGVAL(MCPCIA_PCI_REV(ccp));
166 " CAP Revision %d\n", HORSE_REV(ctl),
167 (SADDLE_TYPE(ctl) & 1)? "Right": "Left", SADDLE_REV(ctl),
168 CAP_REV(ctl));
244 uint32_t ctl; local in function:mcpcia_init0
272 ctl = REGVAL(MCPCIA_WHOAMI(ccp));
273 mcbus_primary.mcbus_cpu_mid = MCBUS_CPU_MID(ctl);
274 if ((MCBUS_CPU_INFO(ctl) & CPU_Fill_Err) == 0 &
300 volatile uint32_t ctl; local in function:mcpcia_config_cleanup
[all...] |
| dwlpx.c | 80 uint32_t ctl; local in function:dwlpxmatch
91 if (badaddr(KV(PCIA_CTL(1) + ls), sizeof (ctl)) != 0) {
184 uint32_t ctl; local in function:dwlpx_init
199 sizeof (ctl)) != 0) {
225 ctl = REGVAL(PCIA_PRESENT + ccp->cc_sysbase);
234 } else if ((ctl >> PCIA_PRESENT_REVSHIFT) & PCIA_PRESENT_REVMASK) {
266 ctl = REGVAL(PCIA_CTL(i) + ccp->cc_sysbase);
267 ctl &= 0x0fffffff;
268 ctl &= ~(PCIA_CTL_MHAE(0x1f) | PCIA_CTL_IHAE(0x1f));
273 ctl |= PCIA_CTL_RMMENA | PCIA_CTL_RMMARB
[all...] |
| /src/sys/arch/news68k/dev/ |
| dmac_0266.h | 30 volatile uint32_t ctl; /* Control Register */ member in struct:dma_regs
|
| dmac_0266.h | 30 volatile uint32_t ctl; /* Control Register */ member in struct:dma_regs
|
