| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn21/ |
| amdgpu_dcn21_hubp.c | 87 uint32_t cur_value; local in function:apply_DEDCN21_142_wa_for_hostvm_deadline
89 REG_GET(VBLANK_PARAMETERS_5, REFCYC_PER_VM_GROUP_VBLANK, &cur_value);
90 if (cur_value > dlg_attr->refcyc_per_vm_group_vblank)
96 &cur_value);
97 if (cur_value > dlg_attr->refcyc_per_vm_req_vblank)
101 REG_GET(FLIP_PARAMETERS_3, REFCYC_PER_VM_GROUP_FLIP, &cur_value);
102 if (cur_value > dlg_attr->refcyc_per_vm_group_flip)
106 REG_GET(FLIP_PARAMETERS_4, REFCYC_PER_VM_REQ_FLIP, &cur_value);
107 if (cur_value > dlg_attr->refcyc_per_vm_req_flip)
|
| amdgpu_dcn21_hubp.c | 87 uint32_t cur_value; local in function:apply_DEDCN21_142_wa_for_hostvm_deadline
89 REG_GET(VBLANK_PARAMETERS_5, REFCYC_PER_VM_GROUP_VBLANK, &cur_value);
90 if (cur_value > dlg_attr->refcyc_per_vm_group_vblank)
96 &cur_value);
97 if (cur_value > dlg_attr->refcyc_per_vm_req_vblank)
101 REG_GET(FLIP_PARAMETERS_3, REFCYC_PER_VM_GROUP_FLIP, &cur_value);
102 if (cur_value > dlg_attr->refcyc_per_vm_group_flip)
106 REG_GET(FLIP_PARAMETERS_4, REFCYC_PER_VM_REQ_FLIP, &cur_value);
107 if (cur_value > dlg_attr->refcyc_per_vm_req_flip)
|
| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/ |
| amdgpu_smu_v12_0.c | 69 uint32_t cur_value, i; local in function:smu_v12_0_wait_for_response
72 cur_value = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);
73 if ((cur_value & MP1_C2PMSG_90__CONTENT_MASK) != 0)
74 return cur_value == 0x1 ? 0 : -EIO;
|
| amdgpu_smu_v12_0.c | 69 uint32_t cur_value, i; local in function:smu_v12_0_wait_for_response
72 cur_value = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);
73 if ((cur_value & MP1_C2PMSG_90__CONTENT_MASK) != 0)
74 return cur_value == 0x1 ? 0 : -EIO;
|
| amdgpu_renoir_ppt.c | 247 uint32_t cur_value = 0, value = 0, count = 0, min = 0, max = 0; local in function:renoir_print_clk_levels
264 cur_value = metrics.ClockFrequency[CLOCK_GFXCLK];
268 if (cur_value == max)
270 else if (cur_value == min)
278 i == 1 ? cur_value : RENOIR_UMD_PSTATE_GFXCLK,
286 cur_value = metrics.ClockFrequency[CLOCK_SOCCLK];
290 cur_value = metrics.ClockFrequency[CLOCK_UMCCLK];
294 cur_value = metrics.ClockFrequency[CLOCK_DCFCLK];
298 cur_value = metrics.ClockFrequency[CLOCK_FCLK];
307 cur_value == value ? "*" : "")
[all...] |
| amdgpu_renoir_ppt.c | 247 uint32_t cur_value = 0, value = 0, count = 0, min = 0, max = 0; local in function:renoir_print_clk_levels
264 cur_value = metrics.ClockFrequency[CLOCK_GFXCLK];
268 if (cur_value == max)
270 else if (cur_value == min)
278 i == 1 ? cur_value : RENOIR_UMD_PSTATE_GFXCLK,
286 cur_value = metrics.ClockFrequency[CLOCK_SOCCLK];
290 cur_value = metrics.ClockFrequency[CLOCK_UMCCLK];
294 cur_value = metrics.ClockFrequency[CLOCK_DCFCLK];
298 cur_value = metrics.ClockFrequency[CLOCK_FCLK];
307 cur_value == value ? "*" : "")
[all...] |
| amdgpu_navi10_ppt.c | 768 uint32_t cur_value = 0, value = 0, count = 0; local in function:navi10_print_clk_levels
790 ret = smu_get_current_clk_freq(smu, clk_type, &cur_value);
795 cur_value = cur_value / 100;
808 cur_value == value ? "*" : "");
818 freq_values[1] = cur_value;
819 mark_index = cur_value == freq_values[0] ? 0 :
820 cur_value == freq_values[2] ? 2 : 1;
|
| amdgpu_smu_v11_0.c | 85 uint32_t cur_value, i, timeout = adev->usec_timeout * 10; local in function:smu_v11_0_wait_for_response
88 cur_value = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);
89 if ((cur_value & MP1_C2PMSG_90__CONTENT_MASK) != 0)
90 return cur_value == 0x1 ? 0 : -EIO;
|
| amdgpu_navi10_ppt.c | 768 uint32_t cur_value = 0, value = 0, count = 0; local in function:navi10_print_clk_levels
790 ret = smu_get_current_clk_freq(smu, clk_type, &cur_value);
795 cur_value = cur_value / 100;
808 cur_value == value ? "*" : "");
818 freq_values[1] = cur_value;
819 mark_index = cur_value == freq_values[0] ? 0 :
820 cur_value == freq_values[2] ? 2 : 1;
|
| amdgpu_smu_v11_0.c | 85 uint32_t cur_value, i, timeout = adev->usec_timeout * 10; local in function:smu_v11_0_wait_for_response
88 cur_value = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);
89 if ((cur_value & MP1_C2PMSG_90__CONTENT_MASK) != 0)
90 return cur_value == 0x1 ? 0 : -EIO;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/ |
| amdgpu_smu_helper.c | 118 uint32_t cur_value; local in function:phm_wait_on_register
126 cur_value = cgs_read_register(hwmgr->device, index);
127 if ((cur_value & mask) == (value & mask))
164 uint32_t cur_value; local in function:phm_wait_for_register_unequal
170 cur_value = cgs_read_register(hwmgr->device,
172 if ((cur_value & mask) != (value & mask))
|
| amdgpu_smu_helper.c | 118 uint32_t cur_value; local in function:phm_wait_on_register
126 cur_value = cgs_read_register(hwmgr->device, index);
127 if ((cur_value & mask) == (value & mask))
164 uint32_t cur_value; local in function:phm_wait_for_register_unequal
170 cur_value = cgs_read_register(hwmgr->device,
172 if ((cur_value & mask) != (value & mask))
|
| /src/usr.sbin/envstat/ |
| envstat.c | 71 int32_t cur_value; member in struct:envsys_sensor
722 sensor->cur_value = prop_number_signed_value(obj1);
813 if (sensor->cur_value > stats->max)
814 stats->max = sensor->cur_value;
816 if (sensor->cur_value < stats->min)
817 stats->min = sensor->cur_value;
821 (sensor->cur_value + stats->max + stats->min) / 3;
1017 sensor->cur_value ? "TRUE" : "FALSE");
1045 PRINTTEMP(sensor->cur_value);
1068 (void)printf("%s%*u", sep, flen, sensor->cur_value);
[all...] |
| envstat.c | 71 int32_t cur_value; member in struct:envsys_sensor
722 sensor->cur_value = prop_number_signed_value(obj1);
813 if (sensor->cur_value > stats->max)
814 stats->max = sensor->cur_value;
816 if (sensor->cur_value < stats->min)
817 stats->min = sensor->cur_value;
821 (sensor->cur_value + stats->max + stats->min) / 3;
1017 sensor->cur_value ? "TRUE" : "FALSE");
1045 PRINTTEMP(sensor->cur_value);
1068 (void)printf("%s%*u", sep, flen, sensor->cur_value);
[all...] |
