| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_uvd.c | 986 unsigned vclk_div, dclk_div, score; local in function:radeon_uvd_calc_upll_dividers
1003 dclk_div = radeon_uvd_calc_upll_post_div(vco_freq, dclk,
1005 if (dclk_div > pd_max)
1009 score = vclk - (vco_freq / vclk_div) + dclk - (vco_freq / dclk_div);
1015 *optimal_dclk_div = dclk_div;
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| radeon_rv770.c | 58 unsigned fb_div = 0, vclk_div = 0, dclk_div = 0; local in function:rv770_set_uvd_clocks
78 &fb_div, &vclk_div, &dclk_div);
84 dclk_div -= 1;
108 UPLL_SW_HILEN2(dclk_div >> 1) |
109 UPLL_SW_LOLEN2((dclk_div >> 1) + (dclk_div & 1)),
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| radeon_uvd.c | 986 unsigned vclk_div, dclk_div, score; local in function:radeon_uvd_calc_upll_dividers
1003 dclk_div = radeon_uvd_calc_upll_post_div(vco_freq, dclk,
1005 if (dclk_div > pd_max)
1009 score = vclk - (vco_freq / vclk_div) + dclk - (vco_freq / dclk_div);
1015 *optimal_dclk_div = dclk_div;
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| radeon_rv770.c | 58 unsigned fb_div = 0, vclk_div = 0, dclk_div = 0; local in function:rv770_set_uvd_clocks
78 &fb_div, &vclk_div, &dclk_div);
84 dclk_div -= 1;
108 UPLL_SW_HILEN2(dclk_div >> 1) |
109 UPLL_SW_LOLEN2((dclk_div >> 1) + (dclk_div & 1)),
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| radeon_r600.c | 212 unsigned fb_div = 0, ref_div, vclk_div = 0, dclk_div = 0; local in function:r600_set_uvd_clocks
241 &fb_div, &vclk_div, &dclk_div);
270 UPLL_SW_HILEN2(dclk_div >> 1) |
271 UPLL_SW_LOLEN2((dclk_div >> 1) + (dclk_div & 1)) |
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| radeon_r600.c | 212 unsigned fb_div = 0, ref_div, vclk_div = 0, dclk_div = 0; local in function:r600_set_uvd_clocks
241 &fb_div, &vclk_div, &dclk_div);
270 UPLL_SW_HILEN2(dclk_div >> 1) |
271 UPLL_SW_LOLEN2((dclk_div >> 1) + (dclk_div & 1)) |
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| radeon_evergreen.c | 1200 unsigned fb_div = 0, vclk_div = 0, dclk_div = 0; local in function:evergreen_set_uvd_clocks
1219 &fb_div, &vclk_div, &dclk_div);
1258 UPLL_PDIV_A(vclk_div) | UPLL_PDIV_B(dclk_div),
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| radeon_evergreen.c | 1200 unsigned fb_div = 0, vclk_div = 0, dclk_div = 0; local in function:evergreen_set_uvd_clocks
1219 &fb_div, &vclk_div, &dclk_div);
1258 UPLL_PDIV_A(vclk_div) | UPLL_PDIV_B(dclk_div),
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| radeon_si.c | 7013 unsigned fb_div = 0, vclk_div = 0, dclk_div = 0; local in function:si_set_uvd_clocks
7031 &fb_div, &vclk_div, &dclk_div);
7072 UPLL_PDIV_A(vclk_div) | UPLL_PDIV_B(dclk_div),
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| radeon_si.c | 7013 unsigned fb_div = 0, vclk_div = 0, dclk_div = 0; local in function:si_set_uvd_clocks
7031 &fb_div, &vclk_div, &dclk_div);
7072 UPLL_PDIV_A(vclk_div) | UPLL_PDIV_B(dclk_div),
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