| /src/sys/external/bsd/drm2/dist/drm/i915/ |
| intel_pm.c | 3131 /* LP0 watermarks always use 1/2 DDB partitioning */
3880 struct skl_ddb_allocation *ddb)
3903 ddb->enabled_slices = 2;
3905 ddb->enabled_slices = 1;
3916 struct skl_ddb_allocation *ddb,
3942 *num_active, ddb);
3957 *alloc = to_intel_crtc_state(for_crtc->state)->wm.skl.ddb;
3962 * Watermark/ddb requirement highly depends upon width of the
3963 * framebuffer, So instead of allocating DDB equally among pipes
3964 * distribute DDB based on resolution/width of the display
5137 const struct skl_ddb_entry *ddb = local in function:skl_write_cursor_wm
5244 struct skl_ddb_allocation *ddb = &state->wm_results.ddb; local in function:skl_compute_ddb
5731 struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb; local in function:skl_wm_get_hw_state
[all...] |
| intel_pm.c | 3131 /* LP0 watermarks always use 1/2 DDB partitioning */
3880 struct skl_ddb_allocation *ddb)
3903 ddb->enabled_slices = 2;
3905 ddb->enabled_slices = 1;
3916 struct skl_ddb_allocation *ddb,
3942 *num_active, ddb);
3957 *alloc = to_intel_crtc_state(for_crtc->state)->wm.skl.ddb;
3962 * Watermark/ddb requirement highly depends upon width of the
3963 * framebuffer, So instead of allocating DDB equally among pipes
3964 * distribute DDB based on resolution/width of the display
5137 const struct skl_ddb_entry *ddb = local in function:skl_write_cursor_wm
5244 struct skl_ddb_allocation *ddb = &state->wm_results.ddb; local in function:skl_compute_ddb
5731 struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb; local in function:skl_wm_get_hw_state
[all...] |
| i915_drv.h | 817 struct skl_ddb_allocation ddb; member in struct:skl_ddb_values
1232 * Set during HW readout of watermarks/DDB. Some platforms
|
| i915_drv.h | 817 struct skl_ddb_allocation ddb; member in struct:skl_ddb_values
1232 * Set during HW readout of watermarks/DDB. Some platforms
|
| /src/sys/external/bsd/drm2/dist/drm/i915/display/ |
| intel_display_types.h | 740 struct skl_ddb_entry ddb; member in struct:intel_crtc_wm_state::__anonde7c4d45070a::__anonde7c4d450908
|
| intel_display_types.h | 740 struct skl_ddb_entry ddb; member in struct:intel_crtc_wm_state::__anonde7c4d45070a::__anonde7c4d450908
|
| intel_display.c | 13764 struct skl_ddb_allocation ddb; member in struct:verify_wm_state::skl_hw_state
13785 skl_ddb_get_hw_state(dev_priv, &hw->ddb);
13786 sw_ddb = &dev_priv->wm.skl_hw.ddb;
13789 hw->ddb.enabled_slices != sw_ddb->enabled_slices)
13792 hw->ddb.enabled_slices);
13829 /* DDB */
13834 DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
13843 * If the cursor plane isn't active, we may not have updated it's ddb
13844 * allocation. In that case since the ddb allocation will be updated
13881 /* DDB */
[all...] |
| intel_display.c | 13764 struct skl_ddb_allocation ddb; member in struct:verify_wm_state::skl_hw_state
13785 skl_ddb_get_hw_state(dev_priv, &hw->ddb);
13786 sw_ddb = &dev_priv->wm.skl_hw.ddb;
13789 hw->ddb.enabled_slices != sw_ddb->enabled_slices)
13792 hw->ddb.enabled_slices);
13829 /* DDB */
13834 DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
13843 * If the cursor plane isn't active, we may not have updated it's ddb
13844 * allocation. In that case since the ddb allocation will be updated
13881 /* DDB */
[all...] |
