| /src/sys/arch/arm/nvidia/ |
| tegra124_cpu.c | 86 u_int divm; member in struct:tegra124_cpufreq_rate
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| tegra124_cpu.c | 86 u_int divm; member in struct:tegra124_cpufreq_rate
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| tegra124_car.c | 1025 u_int divm, divn, divp; local in function:tegra124_car_clock_get_rate_pll
1037 divm = __SHIFTOUT(base, tpll->divm_mask);
1046 return rate / (divm << divp);
1067 const u_int divm = 1; local in function:tegra124_car_clock_set_rate_pll
1084 base |= __SHIFTIN(divm, CAR_PLLX_BASE_DIVM);
1107 const u_int divm = 1; local in function:tegra124_car_clock_set_rate_pll
1113 __SHIFTIN(divm, CAR_PLLD2_BASE_DIVM) |
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| tegra210_car.c | 1147 u_int divm, divn, divp; local in function:tegra210_car_clock_get_rate_pll
1159 divm = __SHIFTOUT(base, tpll->divm_mask);
1168 divm *= __SHIFTOUT(base, tpll->divp_mask);
1174 return rate / (divm << divp);
1195 const u_int divm = 1; local in function:tegra210_car_clock_set_rate_pll
1212 base |= __SHIFTIN(divm, CAR_PLLX_BASE_DIVM);
1235 const u_int divm = 1; local in function:tegra210_car_clock_set_rate_pll
1241 __SHIFTIN(divm, CAR_PLLD2_BASE_DIVM) |
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| tegra124_car.c | 1025 u_int divm, divn, divp; local in function:tegra124_car_clock_get_rate_pll
1037 divm = __SHIFTOUT(base, tpll->divm_mask);
1046 return rate / (divm << divp);
1067 const u_int divm = 1; local in function:tegra124_car_clock_set_rate_pll
1084 base |= __SHIFTIN(divm, CAR_PLLX_BASE_DIVM);
1107 const u_int divm = 1; local in function:tegra124_car_clock_set_rate_pll
1113 __SHIFTIN(divm, CAR_PLLD2_BASE_DIVM) |
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| tegra210_car.c | 1147 u_int divm, divn, divp; local in function:tegra210_car_clock_get_rate_pll
1159 divm = __SHIFTOUT(base, tpll->divm_mask);
1168 divm *= __SHIFTOUT(base, tpll->divp_mask);
1174 return rate / (divm << divp);
1195 const u_int divm = 1; local in function:tegra210_car_clock_set_rate_pll
1212 base |= __SHIFTIN(divm, CAR_PLLX_BASE_DIVM);
1235 const u_int divm = 1; local in function:tegra210_car_clock_set_rate_pll
1241 __SHIFTIN(divm, CAR_PLLD2_BASE_DIVM) |
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