| /src/sys/external/bsd/drm2/dist/drm/i915/display/ |
| intel_dp_aux_backlight.c | 187 u8 dpcd_buf, new_dpcd_buf, edp_backlight_mode; local in function:intel_dp_aux_enable_backlight
190 DP_EDP_BACKLIGHT_MODE_SET_REGISTER, &dpcd_buf) != 1) {
196 new_dpcd_buf = dpcd_buf;
197 edp_backlight_mode = dpcd_buf & DP_EDP_BACKLIGHT_CONTROL_MODE_MASK;
217 if (new_dpcd_buf != dpcd_buf) {
|
| intel_dp_aux_backlight.c | 187 u8 dpcd_buf, new_dpcd_buf, edp_backlight_mode; local in function:intel_dp_aux_enable_backlight
190 DP_EDP_BACKLIGHT_MODE_SET_REGISTER, &dpcd_buf) != 1) {
196 new_dpcd_buf = dpcd_buf;
197 edp_backlight_mode = dpcd_buf & DP_EDP_BACKLIGHT_CONTROL_MODE_MASK;
217 if (new_dpcd_buf != dpcd_buf) {
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/ |
| amdgpu_dc_link_dp.c | 538 uint8_t dpcd_buf[6] = {0}; local in function:get_lane_status_and_drive_settings
555 (uint8_t *)(dpcd_buf),
556 sizeof(dpcd_buf));
563 get_nibble_at_index(&dpcd_buf[0], lane);
565 get_nibble_at_index(&dpcd_buf[lane_adjust_offset], lane);
568 ln_status_updated->raw = dpcd_buf[2];
575 lane01_status_address, dpcd_buf[0],
576 lane01_status_address + 1, dpcd_buf[1]);
580 lane01_status_address, dpcd_buf[0],
581 lane01_status_address + 1, dpcd_buf[1])
[all...] |
| amdgpu_dc_link_dp.c | 538 uint8_t dpcd_buf[6] = {0}; local in function:get_lane_status_and_drive_settings
555 (uint8_t *)(dpcd_buf),
556 sizeof(dpcd_buf));
563 get_nibble_at_index(&dpcd_buf[0], lane);
565 get_nibble_at_index(&dpcd_buf[lane_adjust_offset], lane);
568 ln_status_updated->raw = dpcd_buf[2];
575 lane01_status_address, dpcd_buf[0],
576 lane01_status_address + 1, dpcd_buf[1]);
580 lane01_status_address, dpcd_buf[0],
581 lane01_status_address + 1, dpcd_buf[1])
[all...] |
