| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn20/ |
| amdgpu_dcn20_clk_mgr.c | 113 clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz;
115 int dpp_inst, dppclk_khz, prev_dppclk_khz; local in function:dcn20_update_clocks_update_dpp_dto
121 dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;
123 prev_dppclk_khz = clk_mgr->base.ctx->dc->current_state->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;
125 if ((prev_dppclk_khz > dppclk_khz && safe_to_lower) || prev_dppclk_khz < dppclk_khz) {
127 clk_mgr->dccg, dpp_inst, dppclk_khz);
135 * clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dppclk_khz;
234 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz))
[all...] |
| amdgpu_dcn20_clk_mgr.c | 113 clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz;
115 int dpp_inst, dppclk_khz, prev_dppclk_khz; local in function:dcn20_update_clocks_update_dpp_dto
121 dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;
123 prev_dppclk_khz = clk_mgr->base.ctx->dc->current_state->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;
125 if ((prev_dppclk_khz > dppclk_khz && safe_to_lower) || prev_dppclk_khz < dppclk_khz) {
127 clk_mgr->dccg, dpp_inst, dppclk_khz);
135 * clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dppclk_khz;
234 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz))
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/ |
| core_types.h | 226 int dppclk_khz; member in struct:dcn_fe_bandwidth
|
| core_types.h | 226 int dppclk_khz; member in struct:dcn_fe_bandwidth
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/ |
| dc.h | 279 int dppclk_khz; member in struct:dc_clocks
296 int bw_dppclk_khz; /*a copy of dppclk_khz*/
|
| dc.h | 279 int dppclk_khz; member in struct:dc_clocks
296 int bw_dppclk_khz; /*a copy of dppclk_khz*/
|
