| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/ |
| amdgpu_dml1_display_rq_dlg_calc.c | 605 unsigned int dpte_group_width; local in function:get_surf_rq_param
799 dpte_group_width = 0;
905 dpte_group_width = 1 << log2_dpte_group_width;
907 /* since dpte groups are only aligned to dpte_req_width and not dpte_group_width,
911 (double) dpte_row_width_ub / dpte_group_width,
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| amdgpu_dml1_display_rq_dlg_calc.c | 605 unsigned int dpte_group_width; local in function:get_surf_rq_param
799 dpte_group_width = 0;
905 dpte_group_width = 1 << log2_dpte_group_width;
907 /* since dpte groups are only aligned to dpte_req_width and not dpte_group_width,
911 (double) dpte_row_width_ub / dpte_group_width,
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| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/dcn20/ |
| amdgpu_display_rq_dlg_calc_20.c | 399 unsigned int dpte_group_width = 0; local in function:get_meta_and_pte_attr
663 dpte_group_width = 1 << log2_dpte_group_width;
665 // since dpte groups are only aligned to dpte_req_width and not dpte_group_width,
667 rq_dlg_param->dpte_groups_per_row_ub = dml_ceil((double) dpte_row_width_ub / dpte_group_width,
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| amdgpu_display_rq_dlg_calc_20v2.c | 399 unsigned int dpte_group_width = 0; local in function:get_meta_and_pte_attr
663 dpte_group_width = 1 << log2_dpte_group_width;
665 // since dpte groups are only aligned to dpte_req_width and not dpte_group_width,
667 rq_dlg_param->dpte_groups_per_row_ub = dml_ceil((double) dpte_row_width_ub / dpte_group_width,
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| amdgpu_display_rq_dlg_calc_20.c | 399 unsigned int dpte_group_width = 0; local in function:get_meta_and_pte_attr
663 dpte_group_width = 1 << log2_dpte_group_width;
665 // since dpte groups are only aligned to dpte_req_width and not dpte_group_width,
667 rq_dlg_param->dpte_groups_per_row_ub = dml_ceil((double) dpte_row_width_ub / dpte_group_width,
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| amdgpu_display_rq_dlg_calc_20v2.c | 399 unsigned int dpte_group_width = 0; local in function:get_meta_and_pte_attr
663 dpte_group_width = 1 << log2_dpte_group_width;
665 // since dpte groups are only aligned to dpte_req_width and not dpte_group_width,
667 rq_dlg_param->dpte_groups_per_row_ub = dml_ceil((double) dpte_row_width_ub / dpte_group_width,
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| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/dcn21/ |
| amdgpu_display_rq_dlg_calc_21.c | 390 unsigned int dpte_group_width = 0; local in function:get_meta_and_pte_attr
670 dpte_group_width = 1 << log2_dpte_group_width;
672 // since dpte groups are only aligned to dpte_req_width and not dpte_group_width,
675 (double) dpte_row_width_ub / dpte_group_width,
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| amdgpu_display_rq_dlg_calc_21.c | 390 unsigned int dpte_group_width = 0; local in function:get_meta_and_pte_attr
670 dpte_group_width = 1 << log2_dpte_group_width;
672 // since dpte groups are only aligned to dpte_req_width and not dpte_group_width,
675 (double) dpte_row_width_ub / dpte_group_width,
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