| /src/sys/external/bsd/drm2/dist/drm/i915/display/ |
| intel_dsb.c | 20 * DOC: DSB
22 * A DSB (Display State Buffer) is a queue of MMIO instructions in the memory
23 * which can be offloaded to DSB HW in Display Controller. DSB HW is a DMA
24 * engine that can be programmed to download the DSB from memory.
27 * faster. DSB Support added from Gen12 Intel graphics based platform.
29 * DSB's can access only the pipe, plane, and transcoder Data Island Packet
32 * DSB HW can support only register writes (both indexed and direct MMIO
33 * writes). There are no registers reads possible with DSB HW engine.
36 /* DSB opcodes. *
109 struct intel_dsb *dsb = &crtc->dsb; local in function:intel_dsb_get
[all...] |
| intel_dsb.c | 20 * DOC: DSB
22 * A DSB (Display State Buffer) is a queue of MMIO instructions in the memory
23 * which can be offloaded to DSB HW in Display Controller. DSB HW is a DMA
24 * engine that can be programmed to download the DSB from memory.
27 * faster. DSB Support added from Gen12 Intel graphics based platform.
29 * DSB's can access only the pipe, plane, and transcoder Data Island Packet
32 * DSB HW can support only register writes (both indexed and direct MMIO
33 * writes). There are no registers reads possible with DSB HW engine.
36 /* DSB opcodes. *
109 struct intel_dsb *dsb = &crtc->dsb; local in function:intel_dsb_get
[all...] |
| intel_dsb.c | 20 * DOC: DSB
22 * A DSB (Display State Buffer) is a queue of MMIO instructions in the memory
23 * which can be offloaded to DSB HW in Display Controller. DSB HW is a DMA
24 * engine that can be programmed to download the DSB from memory.
27 * faster. DSB Support added from Gen12 Intel graphics based platform.
29 * DSB's can access only the pipe, plane, and transcoder Data Island Packet
32 * DSB HW can support only register writes (both indexed and direct MMIO
33 * writes). There are no registers reads possible with DSB HW engine.
36 /* DSB opcodes. *
109 struct intel_dsb *dsb = &crtc->dsb; local in function:intel_dsb_get
[all...] |
| intel_color.c | 635 struct intel_dsb *dsb = intel_dsb_get(crtc); local in function:ivb_load_lut_ext_max
639 intel_dsb_reg_write(dsb, PREC_PAL_EXT_GC_MAX(pipe, 0), 1 << 16);
640 intel_dsb_reg_write(dsb, PREC_PAL_EXT_GC_MAX(pipe, 1), 1 << 16);
641 intel_dsb_reg_write(dsb, PREC_PAL_EXT_GC_MAX(pipe, 2), 1 << 16);
649 intel_dsb_reg_write(dsb, PREC_PAL_EXT2_GC_MAX(pipe, 0),
651 intel_dsb_reg_write(dsb, PREC_PAL_EXT2_GC_MAX(pipe, 1),
653 intel_dsb_reg_write(dsb, PREC_PAL_EXT2_GC_MAX(pipe, 2),
657 intel_dsb_put(dsb);
817 struct intel_dsb *dsb = intel_dsb_get(crtc); local in function:icl_load_gcmax
821 intel_dsb_reg_write(dsb, PREC_PAL_GC_MAX(pipe, 0), color->red)
833 struct intel_dsb *dsb = intel_dsb_get(crtc); local in function:icl_program_gamma_superfine_segment
866 struct intel_dsb *dsb = intel_dsb_get(crtc); local in function:icl_program_gamma_multi_segment
920 struct intel_dsb *dsb = intel_dsb_get(crtc); local in function:icl_load_luts
[all...] |
| intel_color.c | 635 struct intel_dsb *dsb = intel_dsb_get(crtc); local in function:ivb_load_lut_ext_max
639 intel_dsb_reg_write(dsb, PREC_PAL_EXT_GC_MAX(pipe, 0), 1 << 16);
640 intel_dsb_reg_write(dsb, PREC_PAL_EXT_GC_MAX(pipe, 1), 1 << 16);
641 intel_dsb_reg_write(dsb, PREC_PAL_EXT_GC_MAX(pipe, 2), 1 << 16);
649 intel_dsb_reg_write(dsb, PREC_PAL_EXT2_GC_MAX(pipe, 0),
651 intel_dsb_reg_write(dsb, PREC_PAL_EXT2_GC_MAX(pipe, 1),
653 intel_dsb_reg_write(dsb, PREC_PAL_EXT2_GC_MAX(pipe, 2),
657 intel_dsb_put(dsb);
817 struct intel_dsb *dsb = intel_dsb_get(crtc); local in function:icl_load_gcmax
821 intel_dsb_reg_write(dsb, PREC_PAL_GC_MAX(pipe, 0), color->red)
833 struct intel_dsb *dsb = intel_dsb_get(crtc); local in function:icl_program_gamma_superfine_segment
866 struct intel_dsb *dsb = intel_dsb_get(crtc); local in function:icl_program_gamma_multi_segment
920 struct intel_dsb *dsb = intel_dsb_get(crtc); local in function:icl_load_luts
[all...] |
| intel_color.c | 635 struct intel_dsb *dsb = intel_dsb_get(crtc); local in function:ivb_load_lut_ext_max
639 intel_dsb_reg_write(dsb, PREC_PAL_EXT_GC_MAX(pipe, 0), 1 << 16);
640 intel_dsb_reg_write(dsb, PREC_PAL_EXT_GC_MAX(pipe, 1), 1 << 16);
641 intel_dsb_reg_write(dsb, PREC_PAL_EXT_GC_MAX(pipe, 2), 1 << 16);
649 intel_dsb_reg_write(dsb, PREC_PAL_EXT2_GC_MAX(pipe, 0),
651 intel_dsb_reg_write(dsb, PREC_PAL_EXT2_GC_MAX(pipe, 1),
653 intel_dsb_reg_write(dsb, PREC_PAL_EXT2_GC_MAX(pipe, 2),
657 intel_dsb_put(dsb);
817 struct intel_dsb *dsb = intel_dsb_get(crtc); local in function:icl_load_gcmax
821 intel_dsb_reg_write(dsb, PREC_PAL_GC_MAX(pipe, 0), color->red)
833 struct intel_dsb *dsb = intel_dsb_get(crtc); local in function:icl_program_gamma_superfine_segment
866 struct intel_dsb *dsb = intel_dsb_get(crtc); local in function:icl_program_gamma_multi_segment
920 struct intel_dsb *dsb = intel_dsb_get(crtc); local in function:icl_load_luts
[all...] |
| intel_display_types.h | 1106 /* per pipe DSB related info */
1107 struct intel_dsb dsb; member in struct:intel_crtc
|
| intel_display_types.h | 1106 /* per pipe DSB related info */
1107 struct intel_dsb dsb; member in struct:intel_crtc
|
| intel_display_types.h | 1106 /* per pipe DSB related info */
1107 struct intel_dsb dsb; member in struct:intel_crtc
|
| /src/sys/arch/arm/include/ |
| cpufunc.h | 47 * Options for DMB and DSB:
61 #define dsb(opt) __asm __volatile("dsb " __STRING(opt) : : : "memory") macro
68 #define dsb(opt) \ macro
79 #define dma_r_r() dsb(oshld) // actually r_rw
80 #define dma_w_w() dsb(oshst)
81 #define dma_rw_w() dsb(osh) // actually rw_rw
83 #define dma_r_r() dsb(osh) // actually rw_rw
84 #define dma_w_w() dsb(oshst)
85 #define dma_rw_w() dsb(osh) // actually rw_r
[all...] |
| cpufunc.h | 47 * Options for DMB and DSB:
61 #define dsb(opt) __asm __volatile("dsb " __STRING(opt) : : : "memory") macro
68 #define dsb(opt) \ macro
79 #define dma_r_r() dsb(oshld) // actually r_rw
80 #define dma_w_w() dsb(oshst)
81 #define dma_rw_w() dsb(osh) // actually rw_rw
83 #define dma_r_r() dsb(osh) // actually rw_rw
84 #define dma_w_w() dsb(oshst)
85 #define dma_rw_w() dsb(osh) // actually rw_r
[all...] |
| cpufunc.h | 47 * Options for DMB and DSB:
61 #define dsb(opt) __asm __volatile("dsb " __STRING(opt) : : : "memory") macro
68 #define dsb(opt) \ macro
79 #define dma_r_r() dsb(oshld) // actually r_rw
80 #define dma_w_w() dsb(oshst)
81 #define dma_rw_w() dsb(osh) // actually rw_rw
83 #define dma_r_r() dsb(osh) // actually rw_rw
84 #define dma_w_w() dsb(oshst)
85 #define dma_rw_w() dsb(osh) // actually rw_r
[all...] |
