| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| amdgpu_dcn20_dsc.c | 162 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &s->dsc_clock_en);
232 int dsc_clock_en; local in function:dsc2_enable
238 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &dsc_clock_en);
240 if ((dsc_clock_en || dsc_fw_config) && enabled_opp_pipe != opp_pipe) {
246 DSC_CLOCK_EN, 1);
257 int dsc_clock_en; local in function:dsc2_disable
263 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &dsc_clock_en);
[all...] |
| amdgpu_dcn20_dsc.c | 162 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &s->dsc_clock_en);
232 int dsc_clock_en; local in function:dsc2_enable
238 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &dsc_clock_en);
240 if ((dsc_clock_en || dsc_fw_config) && enabled_opp_pipe != opp_pipe) {
246 DSC_CLOCK_EN, 1);
257 int dsc_clock_en; local in function:dsc2_disable
263 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &dsc_clock_en);
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/hw/ |
| dsc.h | 57 uint32_t dsc_clock_en; member in struct:dcn_dsc_state
|
| dsc.h | 57 uint32_t dsc_clock_en; member in struct:dcn_dsc_state
|
