/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
amdgpu_umc_v6_1.c | 97 uint32_t ecc_err_cnt_sel, ecc_err_cnt_sel_addr; local in function:umc_v6_1_query_correctable_error_count 121 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4); 122 ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_EccErrCntSel, 124 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel); 133 ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_EccErrCntSel, 135 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel); 315 uint32_t ecc_err_cnt_sel, ecc_err_cnt_sel_addr; local in function:umc_v6_1_err_cnt_init_per_channel 333 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4) [all...] |
amdgpu_umc_v6_1.c | 97 uint32_t ecc_err_cnt_sel, ecc_err_cnt_sel_addr; local in function:umc_v6_1_query_correctable_error_count 121 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4); 122 ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_EccErrCntSel, 124 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel); 133 ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_EccErrCntSel, 135 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel); 315 uint32_t ecc_err_cnt_sel, ecc_err_cnt_sel_addr; local in function:umc_v6_1_err_cnt_init_per_channel 333 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4) [all...] |