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Searched defs:eecd (Results 1 - 6 of 6) sorted by relevancy

/src/sys/dev/pci/igc/
igc_i225.c	`32 uint32_t eecd = IGC_READ_REG(hw, IGC_EECD); local in function:igc_init_nvm_params_i225 37 size = (uint16_t)((eecd & IGC_EECD_SIZE_EX_MASK) >> 56 nvm->page_size = eecd & IGC_EECD_ADDR_BITS ? 32 : 8; 57 nvm->address_bits = eecd & IGC_EECD_ADDR_BITS ? 16 : 8;`
igc_i225.c	`32 uint32_t eecd = IGC_READ_REG(hw, IGC_EECD); local in function:igc_init_nvm_params_i225 37 size = (uint16_t)((eecd & IGC_EECD_SIZE_EX_MASK) >> 56 nvm->page_size = eecd & IGC_EECD_ADDR_BITS ? 32 : 8; 57 nvm->address_bits = eecd & IGC_EECD_ADDR_BITS ? 16 : 8;`
igc_i225.c	`32 uint32_t eecd = IGC_READ_REG(hw, IGC_EECD); local in function:igc_init_nvm_params_i225 37 size = (uint16_t)((eecd & IGC_EECD_SIZE_EX_MASK) >> 56 nvm->page_size = eecd & IGC_EECD_ADDR_BITS ? 32 : 8; 57 nvm->address_bits = eecd & IGC_EECD_ADDR_BITS ? 16 : 8;`
/src/sys/dev/pci/
if_wm.c	14299 * Set SPI and FLASH related information from the EECD register. 14312 /* Read the size of NVM from EECD by default / 14508 uint32_t eecd; local in function:wm_nvm_valid_bank_detect_ich8lan 14548 eecd = CSR_READ(sc, WMREG_EECD); 14549 if ((eecd & EECD_SEC1VAL_VALMASK) == EECD_SEC1VAL_VALMASK) { 14550 bank = ((eecd & EECD_SEC1VAL) != 0) ? 1 : 0; 15120 uint32_t eecd = 0; local in function:wm_nvm_is_onboard_eeprom 15124 eecd = CSR_READ(sc, WMREG_EECD); 15127 eecd = ((eecd >> 15) & 0x03) [all...]
if_wm.c	14299 * Set SPI and FLASH related information from the EECD register. 14312 /* Read the size of NVM from EECD by default / 14508 uint32_t eecd; local in function:wm_nvm_valid_bank_detect_ich8lan 14548 eecd = CSR_READ(sc, WMREG_EECD); 14549 if ((eecd & EECD_SEC1VAL_VALMASK) == EECD_SEC1VAL_VALMASK) { 14550 bank = ((eecd & EECD_SEC1VAL) != 0) ? 1 : 0; 15120 uint32_t eecd = 0; local in function:wm_nvm_is_onboard_eeprom 15124 eecd = CSR_READ(sc, WMREG_EECD); 15127 eecd = ((eecd >> 15) & 0x03) [all...]
if_wm.c	14299 * Set SPI and FLASH related information from the EECD register. 14312 /* Read the size of NVM from EECD by default / 14508 uint32_t eecd; local in function:wm_nvm_valid_bank_detect_ich8lan 14548 eecd = CSR_READ(sc, WMREG_EECD); 14549 if ((eecd & EECD_SEC1VAL_VALMASK) == EECD_SEC1VAL_VALMASK) { 14550 bank = ((eecd & EECD_SEC1VAL) != 0) ? 1 : 0; 15120 uint32_t eecd = 0; local in function:wm_nvm_is_onboard_eeprom 15124 eecd = CSR_READ(sc, WMREG_EECD); 15127 eecd = ((eecd >> 15) & 0x03) [all...]

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