| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/engine/disp/ |
| nouveau_nvkm_engine_disp_dp.c | 359 const struct dp_rates *failsafe = NULL, *cfg; local
379 if (!failsafe ||
381 failsafe = cfg;
384 if (failsafe && cfg[1].rate < dataKBps)
388 if (WARN_ON(!failsafe))
402 failsafe->nr, failsafe->bw * 27);
404 for (cfg = nvkm_dp_rates; ret < 0 && cfg <= failsafe; cfg++) {
408 if (cfg != failsafe)
|
| nouveau_nvkm_engine_disp_dp.c | 359 const struct dp_rates *failsafe = NULL, *cfg; local
379 if (!failsafe ||
381 failsafe = cfg;
384 if (failsafe && cfg[1].rate < dataKBps)
388 if (WARN_ON(!failsafe))
402 failsafe->nr, failsafe->bw * 27);
404 for (cfg = nvkm_dp_rates; ret < 0 && cfg <= failsafe; cfg++) {
408 if (cfg != failsafe)
|
| /src/sys/dev/ic/ |
| mlx.c | 1451 int failsafe, i, cmd; local
1456 failsafe = 0;
1461 * Channels will always start again after the failsafe
1465 failsafe = ((mlx->mlx_pause.mp_howlong - time_second) + 5) / 30;
1467 if (failsafe > 0xf) {
1468 failsafe = 0xf;
1486 mlx_make_type2(mc, cmd, (failsafe << 4) | i, 0, 0,
|
| mlx.c | 1451 int failsafe, i, cmd; local
1456 failsafe = 0;
1461 * Channels will always start again after the failsafe
1465 failsafe = ((mlx->mlx_pause.mp_howlong - time_second) + 5) / 30;
1467 if (failsafe > 0xf) {
1468 failsafe = 0xf;
1486 mlx_make_type2(mc, cmd, (failsafe << 4) | i, 0, 0,
|
| /src/sys/external/bsd/drm2/dist/drm/i915/gvt/ |
| gvt.h | 177 bool failsafe; member in struct:intel_vgpu
|
| gvt.h | 177 bool failsafe; member in struct:intel_vgpu
|
