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  /src/sys/arch/arm/rockchip/
rk3399_pmucru.c 184 const u_int fbdiv = __SHIFTOUT(con0, PLL_FBDIV); local in function:rk3399_pmucru_pll_get_rate
193 foutvco = fref / refdiv * fbdiv;
196 foutvco = fref / refdiv * fbdiv + ((fref * fracdiv) >> 24);
229 __SHIFTIN(pll_rate->fbdiv, PLL_FBDIV) |
rk3399_pmucru.c 184 const u_int fbdiv = __SHIFTOUT(con0, PLL_FBDIV); local in function:rk3399_pmucru_pll_get_rate
193 foutvco = fref / refdiv * fbdiv;
196 foutvco = fref / refdiv * fbdiv + ((fref * fracdiv) >> 24);
229 __SHIFTIN(pll_rate->fbdiv, PLL_FBDIV) |
rk3399_pmucru.c 184 const u_int fbdiv = __SHIFTOUT(con0, PLL_FBDIV); local in function:rk3399_pmucru_pll_get_rate
193 foutvco = fref / refdiv * fbdiv;
196 foutvco = fref / refdiv * fbdiv + ((fref * fracdiv) >> 24);
229 __SHIFTIN(pll_rate->fbdiv, PLL_FBDIV) |
rk_cru_pll.c 137 const u_int fbdiv = __SHIFTOUT(con0, PLL_FBDIV); local in function:rk_cru_pll_get_rate
145 foutvco = fref / refdiv * fbdiv;
148 foutvco = fref / refdiv * fbdiv + ((fref * fracdiv) >> 24);
237 __SHIFTIN(pll_rate->fbdiv, PLL_FBDIV) |
rk_cru_pll.c 137 const u_int fbdiv = __SHIFTOUT(con0, PLL_FBDIV); local in function:rk_cru_pll_get_rate
145 foutvco = fref / refdiv * fbdiv;
148 foutvco = fref / refdiv * fbdiv + ((fref * fracdiv) >> 24);
237 __SHIFTIN(pll_rate->fbdiv, PLL_FBDIV) |
rk_cru_pll.c 137 const u_int fbdiv = __SHIFTOUT(con0, PLL_FBDIV); local in function:rk_cru_pll_get_rate
145 foutvco = fref / refdiv * fbdiv;
148 foutvco = fref / refdiv * fbdiv + ((fref * fracdiv) >> 24);
237 __SHIFTIN(pll_rate->fbdiv, PLL_FBDIV) |
rk3399_cru.c 256 const u_int fbdiv = __SHIFTOUT(con0, PLL_FBDIV); local in function:rk3399_cru_pll_get_rate
265 foutvco = fref / refdiv * fbdiv;
268 foutvco = fref / refdiv * fbdiv + ((fref * fracdiv) >> 24);
307 __SHIFTIN(pll_rate->fbdiv, PLL_FBDIV) | (PLL_FBDIV << 16));
rk3399_cru.c 256 const u_int fbdiv = __SHIFTOUT(con0, PLL_FBDIV); local in function:rk3399_cru_pll_get_rate
265 foutvco = fref / refdiv * fbdiv;
268 foutvco = fref / refdiv * fbdiv + ((fref * fracdiv) >> 24);
307 __SHIFTIN(pll_rate->fbdiv, PLL_FBDIV) | (PLL_FBDIV << 16));
rk3399_cru.c 256 const u_int fbdiv = __SHIFTOUT(con0, PLL_FBDIV); local in function:rk3399_cru_pll_get_rate
265 foutvco = fref / refdiv * fbdiv;
268 foutvco = fref / refdiv * fbdiv + ((fref * fracdiv) >> 24);
307 __SHIFTIN(pll_rate->fbdiv, PLL_FBDIV) | (PLL_FBDIV << 16));
rk_cru.h 58 u_int fbdiv; member in struct:rk_cru_pll_rate::__anonf247ef35010a::__anonf247ef350208
77 .fbdiv = (_fbdiv), \
rk_cru.h 58 u_int fbdiv; member in struct:rk_cru_pll_rate::__anonf247ef35010a::__anonf247ef350208
77 .fbdiv = (_fbdiv), \
rk_cru.h 58 u_int fbdiv; member in struct:rk_cru_pll_rate::__anonf247ef35010a::__anonf247ef350208
77 .fbdiv = (_fbdiv), \
  /src/sys/arch/mips/atheros/
ar5315.c 170 const uint32_t fbdiv = AR5315_PLLC_FB_DIV(pllc); local in function:ar5315_get_freqs
176 freqs->freq_pll = (freqs->freq_ref / refdiv) * div2 * fbdiv;
ar5315.c 170 const uint32_t fbdiv = AR5315_PLLC_FB_DIV(pllc); local in function:ar5315_get_freqs
176 freqs->freq_pll = (freqs->freq_ref / refdiv) * div2 * fbdiv;
ar5315.c 170 const uint32_t fbdiv = AR5315_PLLC_FB_DIV(pllc); local in function:ar5315_get_freqs
176 freqs->freq_pll = (freqs->freq_ref / refdiv) * div2 * fbdiv;
  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_rv730_dpm.c 58 u32 fbdiv; local in function:rv730_populate_sclk_value
76 fbdiv = (u32) tmp;
92 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
102 u32 clk_v = ss.percentage * fbdiv / (clk_s * 10000);
radeon_rv740_dpm.c 138 u32 fbdiv; local in function:rv740_populate_sclk_value
150 fbdiv = (u32) tmp;
160 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
170 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
radeon_rv730_dpm.c 58 u32 fbdiv; local in function:rv730_populate_sclk_value
76 fbdiv = (u32) tmp;
92 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
102 u32 clk_v = ss.percentage * fbdiv / (clk_s * 10000);
radeon_rv740_dpm.c 138 u32 fbdiv; local in function:rv740_populate_sclk_value
150 fbdiv = (u32) tmp;
160 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
170 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
radeon_rv730_dpm.c 58 u32 fbdiv; local in function:rv730_populate_sclk_value
76 fbdiv = (u32) tmp;
92 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
102 u32 clk_v = ss.percentage * fbdiv / (clk_s * 10000);
radeon_rv740_dpm.c 138 u32 fbdiv; local in function:rv740_populate_sclk_value
150 fbdiv = (u32) tmp;
160 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
170 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
radeon_rs780_dpm.c 217 u32 fbdiv = (RREG32(CG_SPLL_FUNC_CNTL) & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT; local in function:rs780_preset_starting_fbdiv
219 WREG32_P(FVTHROT_FBDIV_REG1, STARTING_FEEDBACK_DIV(fbdiv),
222 WREG32_P(FVTHROT_FBDIV_REG2, FORCED_FEEDBACK_DIV(fbdiv),
radeon_rs780_dpm.c 217 u32 fbdiv = (RREG32(CG_SPLL_FUNC_CNTL) & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT; local in function:rs780_preset_starting_fbdiv
219 WREG32_P(FVTHROT_FBDIV_REG1, STARTING_FEEDBACK_DIV(fbdiv),
222 WREG32_P(FVTHROT_FBDIV_REG2, FORCED_FEEDBACK_DIV(fbdiv),
radeon_rs780_dpm.c 217 u32 fbdiv = (RREG32(CG_SPLL_FUNC_CNTL) & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT; local in function:rs780_preset_starting_fbdiv
219 WREG32_P(FVTHROT_FBDIV_REG1, STARTING_FEEDBACK_DIV(fbdiv),
222 WREG32_P(FVTHROT_FBDIV_REG2, FORCED_FEEDBACK_DIV(fbdiv),
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/
amdgpu_ci_smumgr.c 312 uint32_t fbdiv; local in function:ci_calculate_sclk_params
322 /* To get FBDIV we need to multiply this by 16384 and divide it by Fref. */
327 fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF;
337 SPLL_FB_DIV, fbdiv);
353 fbdiv / (clk_s * 10000);

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