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  /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/
xenvm-4.2.dts 15 interrupt-parent = <&gic>;
54 gic: interrupt-controller@2c001000 { label
55 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
xenvm-4.2.dts 15 interrupt-parent = <&gic>;
54 gic: interrupt-controller@2c001000 { label
55 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
milbeaut-m10v.dtsi 5 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 interrupt-parent = <&gic>;
58 interrupt-parent = <&gic>;
60 gic: interrupt-controller@1d000000 { label
61 compatible = "arm,cortex-a7-gic";
milbeaut-m10v.dtsi 5 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 interrupt-parent = <&gic>;
58 interrupt-parent = <&gic>;
60 gic: interrupt-controller@1d000000 { label
61 compatible = "arm,cortex-a7-gic";
alpine.dtsi 27 #include <dt-bindings/interrupt-controller/arm-gic.h>
79 interrupt-parent = <&gic>;
94 gic: interrupt-controller@fb001000 { label
95 compatible = "arm,cortex-a15-gic";
157 interrupt-map = <0x4000 0 0 1 &gic 0 43 4>,
158 <0x4800 0 0 1 &gic 0 44 4>;
alpine.dtsi 27 #include <dt-bindings/interrupt-controller/arm-gic.h>
79 interrupt-parent = <&gic>;
94 gic: interrupt-controller@fb001000 { label
95 compatible = "arm,cortex-a15-gic";
157 interrupt-map = <0x4000 0 0 1 &gic 0 43 4>,
158 <0x4800 0 0 1 &gic 0 44 4>;
hip01.dtsi 12 interrupt-parent = <&gic>;
16 gic: interrupt-controller@1e001000 { label
17 compatible = "arm,cortex-a9-gic";
35 interrupt-parent = <&gic>;
  /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/arm/
foundation-v8-gicv2.dtsi 8 gic: interrupt-controller@2c001000 { label
9 compatible = "arm,gic-400", "arm,cortex-a15-gic";
foundation-v8-gicv2.dtsi 8 gic: interrupt-controller@2c001000 { label
9 compatible = "arm,gic-400", "arm,cortex-a15-gic";
foundation-v8-gicv3.dtsi 8 gic: interrupt-controller@2f000000 { label
9 compatible = "arm,gic-v3";
23 compatible = "arm,gic-v3-its";
foundation-v8-gicv3.dtsi 8 gic: interrupt-controller@2f000000 { label
9 compatible = "arm,gic-v3";
23 compatible = "arm,gic-v3-its";
rtsm_ve-aemv8a.dts 13 #include <dt-bindings/interrupt-controller/arm-gic.h>
22 interrupt-parent = <&gic>;
97 gic: interrupt-controller@2c001000 { label
98 compatible = "arm,gic-400", "arm,cortex-a15-gic";
138 interrupt-map = <0 0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
139 <0 0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
140 <0 0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
141 <0 0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
142 <0 0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>
    [all...]
rtsm_ve-aemv8a.dts 13 #include <dt-bindings/interrupt-controller/arm-gic.h>
22 interrupt-parent = <&gic>;
97 gic: interrupt-controller@2c001000 { label
98 compatible = "arm,gic-400", "arm,cortex-a15-gic";
138 interrupt-map = <0 0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
139 <0 0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
140 <0 0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
141 <0 0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
142 <0 0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>
    [all...]
vexpress-v2f-1xv7-ca53x2.dts 15 #include <dt-bindings/interrupt-controller/arm-gic.h>
23 interrupt-parent = <&gic>;
82 gic: interrupt-controller@2c001000 { label
83 compatible = "arm,gic-400";
vexpress-v2f-1xv7-ca53x2.dts 15 #include <dt-bindings/interrupt-controller/arm-gic.h>
23 interrupt-parent = <&gic>;
82 gic: interrupt-controller@2c001000 { label
83 compatible = "arm,gic-400";
  /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/cavium/
thunder2-99xx.dtsi 10 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 interrupt-parent = <&gic>;
58 gic: interrupt-controller@400080000 { label
59 compatible = "arm,gic-v3";
70 gicits: gic-its@40010000 {
71 compatible = "arm,gic-v3-its";
73 reg = <0x04 0x00100000 0x0 0x20000>; /* GIC ITS */
121 <0 0 0 1 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
122 0 0 0 2 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
123 0 0 0 3 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIG
    [all...]
thunder2-99xx.dtsi 10 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 interrupt-parent = <&gic>;
58 gic: interrupt-controller@400080000 { label
59 compatible = "arm,gic-v3";
70 gicits: gic-its@40010000 {
71 compatible = "arm,gic-v3-its";
73 reg = <0x04 0x00100000 0x0 0x20000>; /* GIC ITS */
121 <0 0 0 1 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
122 0 0 0 2 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
123 0 0 0 3 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIG
    [all...]
  /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/marvell/
armada-ap810-ap0.dtsi 8 #include <dt-bindings/interrupt-controller/arm-gic.h>
32 interrupt-parent = <&gic>;
40 interrupt-parent = <&gic>;
42 gic: interrupt-controller@3000000 { label
43 compatible = "arm,gic-v3";
58 compatible = "arm,gic-v3-its";
armada-ap810-ap0.dtsi 8 #include <dt-bindings/interrupt-controller/arm-gic.h>
32 interrupt-parent = <&gic>;
40 interrupt-parent = <&gic>;
42 gic: interrupt-controller@3000000 { label
43 compatible = "arm,gic-v3";
58 compatible = "arm,gic-v3-its";
  /src/sys/external/gpl2/dts/dist/arch/mips/boot/dts/mti/
malta.dts 5 #include <dt-bindings/interrupt-controller/mips-gic.h>
23 gic: interrupt-controller@1bdc0000 { label
24 compatible = "mti,gic";
31 * Declare the interrupt-parent even though the mti,gic
39 compatible = "mti,gic-timer";
50 interrupt-parent = <&gic>;
malta.dts 5 #include <dt-bindings/interrupt-controller/mips-gic.h>
23 gic: interrupt-controller@1bdc0000 { label
24 compatible = "mti,gic";
31 * Declare the interrupt-parent even though the mti,gic
39 compatible = "mti,gic-timer";
50 interrupt-parent = <&gic>;
sead3.dts 8 #include <dt-bindings/interrupt-controller/mips-gic.h>
43 gic: interrupt-controller@1b1c0000 { label
44 compatible = "mti,gic";
51 * Declare the interrupt-parent even though the mti,gic
63 interrupt-parent = <&gic>;
64 interrupts = <GIC_SHARED 0 IRQ_TYPE_LEVEL_HIGH>; /* GIC 0 or CPU 6 */
226 interrupt-parent = <&gic>;
227 interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>; /* GIC 3 or CPU 4 */
241 interrupt-parent = <&gic>;
242 interrupts = <GIC_SHARED 2 IRQ_TYPE_LEVEL_HIGH>; /* GIC 2 or CPU 4 *
    [all...]
sead3.dts 8 #include <dt-bindings/interrupt-controller/mips-gic.h>
43 gic: interrupt-controller@1b1c0000 { label
44 compatible = "mti,gic";
51 * Declare the interrupt-parent even though the mti,gic
63 interrupt-parent = <&gic>;
64 interrupts = <GIC_SHARED 0 IRQ_TYPE_LEVEL_HIGH>; /* GIC 0 or CPU 6 */
226 interrupt-parent = <&gic>;
227 interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>; /* GIC 3 or CPU 4 */
241 interrupt-parent = <&gic>;
242 interrupts = <GIC_SHARED 2 IRQ_TYPE_LEVEL_HIGH>; /* GIC 2 or CPU 4 *
    [all...]
  /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/intel/
keembay-soc.dtsi 8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 interrupt-parent = <&gic>;
53 gic: interrupt-controller@20500000 { label
54 compatible = "arm,gic-v3";
keembay-soc.dtsi 8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 interrupt-parent = <&gic>;
53 gic: interrupt-controller@20500000 { label
54 compatible = "arm,gic-v3";

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1 2 3 4 5 6 7 8 91011>>