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Searched defs:gicc_write (Results 1 - 2 of 2) sorted by relevancy

/src/sys/arch/arm/cortex/
gic.c	137 gicc_write(struct armgic_softc sc, bus_size_t o, uint32_t v) function in typeref:typename:void 231 gicc_write(sc, GICC_PMR, armgic_ipl_to_priority(ipl)); 336 gicc_write(sc, GICC_PMR, armgic_ipl_to_priority(old_ipl)); 390 gicc_write(sc, GICC_PMR, armgic_ipl_to_priority(ipl)); 396 gicc_write(sc, GICC_EOIR, iar); 559 gicc_write(sc, GICC_PMR, armgic_ipl_to_priority(ci->ci_cpl)); // set PMR 560 gicc_write(sc, GICC_CTRL, GICC_CTRL_V1_Enable); // enable interrupt 624 gicc_write(sc, GICC_CTRL, 0); / disable all interrupts */ 627 gicc_write(sc, GICC_PMR, 0xff); 687 gicc_write(sc, GICC_CTRL, GICC_CTRL_V1_Enable); // enable CPU interrupt [all...]
gic.c	137 gicc_write(struct armgic_softc sc, bus_size_t o, uint32_t v) function in typeref:typename:void 231 gicc_write(sc, GICC_PMR, armgic_ipl_to_priority(ipl)); 336 gicc_write(sc, GICC_PMR, armgic_ipl_to_priority(old_ipl)); 390 gicc_write(sc, GICC_PMR, armgic_ipl_to_priority(ipl)); 396 gicc_write(sc, GICC_EOIR, iar); 559 gicc_write(sc, GICC_PMR, armgic_ipl_to_priority(ci->ci_cpl)); // set PMR 560 gicc_write(sc, GICC_CTRL, GICC_CTRL_V1_Enable); // enable interrupt 624 gicc_write(sc, GICC_CTRL, 0); / disable all interrupts */ 627 gicc_write(sc, GICC_PMR, 0xff); 687 gicc_write(sc, GICC_CTRL, GICC_CTRL_V1_Enable); // enable CPU interrupt [all...]

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