| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/ |
| dc_stream.h | 39 int group_size; member in struct:timing_sync_info
|
| dc_stream.h | 39 int group_size; member in struct:timing_sync_info
|
| /src/sys/dev/ic/ |
| cs89x0.c | 689 int group_size; local in function:cs_read_pktpg_from_eeprom
701 group_size = header & 0xF000;
711 offset_max = offset + (group_size << 1);
724 x += group_size + 1;
|
| cs89x0.c | 689 int group_size; local in function:cs_read_pktpg_from_eeprom
701 group_size = header & 0xF000;
711 offset_max = offset + (group_size << 1);
724 x += group_size + 1;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/ |
| amdgpu_dc.c | 962 int group_size = 1; local in function:program_timing_sync
981 pipe_set[group_size] = unsynced_pipes[j];
983 group_size++;
988 for (j = 0; j < group_size; j++) {
999 for (k = 0; k < group_size; k++) {
1003 status->timing_sync_info.group_size = group_size;
1011 for (j = j + 1; j < group_size; j++) {
1013 group_size--;
1014 pipe_set[j] = pipe_set[group_size];
[all...] |
| amdgpu_dc.c | 962 int group_size = 1; local in function:program_timing_sync
981 pipe_set[group_size] = unsynced_pipes[j];
983 group_size++;
988 for (j = 0; j < group_size; j++) {
999 for (k = 0; k < group_size; k++) {
1003 status->timing_sync_info.group_size = group_size;
1011 for (j = j + 1; j < group_size; j++) {
1013 group_size--;
1014 pipe_set[j] = pipe_set[group_size];
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_evergreen_cs.c | 52 u32 group_size; member in struct:evergreen_cs_track
217 palign = MAX(64, track->group_size / surf->bpe);
219 surf->base_align = track->group_size;
239 palign = track->group_size / (8 * surf->bpe * surf->nsamples);
242 surf->base_align = track->group_size;
249 track->group_size, surf->bpe, surf->nsamples);
2754 track->group_size = 256;
2758 track->group_size = 512;
|
| radeon_evergreen_cs.c | 52 u32 group_size; member in struct:evergreen_cs_track
217 palign = MAX(64, track->group_size / surf->bpe);
219 surf->base_align = track->group_size;
239 palign = track->group_size / (8 * surf->bpe * surf->nsamples);
242 surf->base_align = track->group_size;
249 track->group_size, surf->bpe, surf->nsamples);
2754 track->group_size = 256;
2758 track->group_size = 512;
|
| radeon_r600_cs.c | 41 extern void r600_cs_legacy_get_tiling_conf(struct drm_device *dev, u32 *npipes, u32 *nbanks, u32 *group_size);
46 u32 group_size; member in struct:r600_cs_track
246 u32 group_size; member in struct:array_mode_checker
276 *pitch_align = max((u32)64, (u32)(values->group_size / values->blocksize));
279 *base_align = values->group_size;
283 (u32)(values->group_size /
287 *base_align = values->group_size;
291 (u32)((values->group_size * values->nbanks) /
386 array_check.group_size = track->group_size;
[all...] |
| radeon_r600_cs.c | 41 extern void r600_cs_legacy_get_tiling_conf(struct drm_device *dev, u32 *npipes, u32 *nbanks, u32 *group_size);
46 u32 group_size; member in struct:r600_cs_track
246 u32 group_size; member in struct:array_mode_checker
276 *pitch_align = max((u32)64, (u32)(values->group_size / values->blocksize));
279 *base_align = values->group_size;
283 (u32)(values->group_size /
287 *base_align = values->group_size;
291 (u32)((values->group_size * values->nbanks) /
386 array_check.group_size = track->group_size;
[all...] |
