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Searched defs:icsc_regs (Results 1 - 2 of 2) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
amdgpu_dcn20_dpp_cm.c	254 struct color_matrices_reg icsc_regs; local in function:dpp2_program_input_csc 289 icsc_regs.shifts.csc_c11 = dpp->tf_shift->CM_ICSC_C11; 290 icsc_regs.masks.csc_c11 = dpp->tf_mask->CM_ICSC_C11; 291 icsc_regs.shifts.csc_c12 = dpp->tf_shift->CM_ICSC_C12; 292 icsc_regs.masks.csc_c12 = dpp->tf_mask->CM_ICSC_C12; 296 icsc_regs.csc_c11_c12 = REG(CM_ICSC_C11_C12); 297 icsc_regs.csc_c33_c34 = REG(CM_ICSC_C33_C34); 301 icsc_regs.csc_c11_c12 = REG(CM_ICSC_B_C11_C12); 302 icsc_regs.csc_c33_c34 = REG(CM_ICSC_B_C33_C34); 309 &icsc_regs); [all...]
amdgpu_dcn20_dpp_cm.c	254 struct color_matrices_reg icsc_regs; local in function:dpp2_program_input_csc 289 icsc_regs.shifts.csc_c11 = dpp->tf_shift->CM_ICSC_C11; 290 icsc_regs.masks.csc_c11 = dpp->tf_mask->CM_ICSC_C11; 291 icsc_regs.shifts.csc_c12 = dpp->tf_shift->CM_ICSC_C12; 292 icsc_regs.masks.csc_c12 = dpp->tf_mask->CM_ICSC_C12; 296 icsc_regs.csc_c11_c12 = REG(CM_ICSC_C11_C12); 297 icsc_regs.csc_c33_c34 = REG(CM_ICSC_C33_C34); 301 icsc_regs.csc_c11_c12 = REG(CM_ICSC_B_C11_C12); 302 icsc_regs.csc_c33_c34 = REG(CM_ICSC_B_C33_C34); 309 &icsc_regs); [all...]

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