| /src/sys/arch/alpha/alpha/ |
| patch.c | 71 alpha_instruction insn = { local in function:patch_lock_stubs
82 *lock_stub_patch_table[i] = insn.bits;
|
| patch.c | 71 alpha_instruction insn = { local in function:patch_lock_stubs
82 *lock_stub_patch_table[i] = insn.bits;
|
| patch.c | 71 alpha_instruction insn = { local in function:patch_lock_stubs
82 *lock_stub_patch_table[i] = insn.bits;
|
| /src/sys/arch/mips/mips/ |
| kobj_machdep.c | 70 uint32_t *insn; local in function:kobj_reloc
94 insn = (void *)where;
129 KASSERT((*insn & 0x3ffffff) == 0);
130 DPRINTF(" orig insn = 0x%08x\n", *insn);
131 *insn |= addr;
132 DPRINTF(" new insn = 0x%08x\n", *insn);
142 KASSERT((*insn & 0xffff) == 0);
143 DPRINTF(" orig insn = 0x%08x\n", *insn)
[all...] |
| kobj_machdep.c | 70 uint32_t *insn; local in function:kobj_reloc
94 insn = (void *)where;
129 KASSERT((*insn & 0x3ffffff) == 0);
130 DPRINTF(" orig insn = 0x%08x\n", *insn);
131 *insn |= addr;
132 DPRINTF(" new insn = 0x%08x\n", *insn);
142 KASSERT((*insn & 0xffff) == 0);
143 DPRINTF(" orig insn = 0x%08x\n", *insn)
[all...] |
| kobj_machdep.c | 70 uint32_t *insn; local in function:kobj_reloc
94 insn = (void *)where;
129 KASSERT((*insn & 0x3ffffff) == 0);
130 DPRINTF(" orig insn = 0x%08x\n", *insn);
131 *insn |= addr;
132 DPRINTF(" new insn = 0x%08x\n", *insn);
142 KASSERT((*insn & 0xffff) == 0);
143 DPRINTF(" orig insn = 0x%08x\n", *insn)
[all...] |
| /src/sys/arch/aarch64/aarch64/ |
| db_disasm.c | 139 uint32_t insn = 0; local in function:strdisasm
143 size = fetch_arm_insn(pc, spsr, &insn);
147 ".insn 0x%0*x (%s)", size * 2, insn, arch);
|
| db_disasm.c | 139 uint32_t insn = 0; local in function:strdisasm
143 size = fetch_arm_insn(pc, spsr, &insn);
147 ".insn 0x%0*x (%s)", size * 2, insn, arch);
|
| db_disasm.c | 139 uint32_t insn = 0; local in function:strdisasm
143 size = fetch_arm_insn(pc, spsr, &insn);
147 ".insn 0x%0*x (%s)", size * 2, insn, arch);
|
| kobj_machdep.c | 130 uint32_t *insn, immhi, immlo, shift; local in function:kobj_reloc
162 insn = (uint32_t *)where;
193 le32toh(*insn), strdisasm((vaddr_t)insn, 0));
256 *insn = htole32(
257 (le32toh(*insn) & ~__BITS(21,10)) | (val << 10));
278 *insn = htole32((le32toh(*insn) &
302 *insn = htole32((le32toh(*insn) & ~__BITS(25,0)) | val)
[all...] |
| /src/sys/arch/arm/include/ |
| locore.h | 199 uint32_t insn; local in function:read_insn
201 __asm __volatile("ldrt %0, [%1]" : "=&r"(insn) : "r"(va));
203 insn = *(const uint32_t *)va;
206 insn = bswap32(insn);
208 return insn;
218 uint32_t insn; local in function:read_thumb_insn
221 __asm __volatile("ldrht %0, [%1, #0]" : "=&r"(insn) : "r"(va));
223 __asm __volatile("ldrht %0, [%1], #0" : "=&r"(insn) : "r"(va));
225 __asm __volatile("ldrt %0, [%1]" : "=&r"(insn) : "r"(va & ~3))
[all...] |
| locore.h | 199 uint32_t insn; local in function:read_insn
201 __asm __volatile("ldrt %0, [%1]" : "=&r"(insn) : "r"(va));
203 insn = *(const uint32_t *)va;
206 insn = bswap32(insn);
208 return insn;
218 uint32_t insn; local in function:read_thumb_insn
221 __asm __volatile("ldrht %0, [%1, #0]" : "=&r"(insn) : "r"(va));
223 __asm __volatile("ldrht %0, [%1], #0" : "=&r"(insn) : "r"(va));
225 __asm __volatile("ldrt %0, [%1]" : "=&r"(insn) : "r"(va & ~3))
[all...] |
| locore.h | 199 uint32_t insn; local in function:read_insn
201 __asm __volatile("ldrt %0, [%1]" : "=&r"(insn) : "r"(va));
203 insn = *(const uint32_t *)va;
206 insn = bswap32(insn);
208 return insn;
218 uint32_t insn; local in function:read_thumb_insn
221 __asm __volatile("ldrht %0, [%1, #0]" : "=&r"(insn) : "r"(va));
223 __asm __volatile("ldrht %0, [%1], #0" : "=&r"(insn) : "r"(va));
225 __asm __volatile("ldrt %0, [%1]" : "=&r"(insn) : "r"(va & ~3))
[all...] |
| /src/sys/arch/arm/arm/ |
| syscall.c | 97 uint32_t insn; local in function:swi_handler
132 insn = 0xef000000 | SWI_OS_NETBSD | tf->tf_r0;
138 insn = read_insn(tf->tf_pc - INSN_SIZE, true);
160 if ((insn & 0x0f000000) != 0x0f000000) {
170 (*l->l_proc->p_md.md_syscall)(tf, l, insn);
182 syscall(struct trapframe *tf, lwp_t *l, uint32_t insn)
194 const uint32_t os_mask = insn & SWI_OS_MASK;
195 uint32_t code = insn & 0x000fffff;
201 const uint32_t swi = __SHIFTOUT(insn, __BITS(23,0));
217 ksi.ksi_trap = insn;
[all...] |
| syscall.c | 97 uint32_t insn; local in function:swi_handler
132 insn = 0xef000000 | SWI_OS_NETBSD | tf->tf_r0;
138 insn = read_insn(tf->tf_pc - INSN_SIZE, true);
160 if ((insn & 0x0f000000) != 0x0f000000) {
170 (*l->l_proc->p_md.md_syscall)(tf, l, insn);
182 syscall(struct trapframe *tf, lwp_t *l, uint32_t insn)
194 const uint32_t os_mask = insn & SWI_OS_MASK;
195 uint32_t code = insn & 0x000fffff;
201 const uint32_t swi = __SHIFTOUT(insn, __BITS(23,0));
217 ksi.ksi_trap = insn;
[all...] |
| syscall.c | 97 uint32_t insn; local in function:swi_handler
132 insn = 0xef000000 | SWI_OS_NETBSD | tf->tf_r0;
138 insn = read_insn(tf->tf_pc - INSN_SIZE, true);
160 if ((insn & 0x0f000000) != 0x0f000000) {
170 (*l->l_proc->p_md.md_syscall)(tf, l, insn);
182 syscall(struct trapframe *tf, lwp_t *l, uint32_t insn)
194 const uint32_t os_mask = insn & SWI_OS_MASK;
195 uint32_t code = insn & 0x000fffff;
201 const uint32_t swi = __SHIFTOUT(insn, __BITS(23,0));
217 ksi.ksi_trap = insn;
[all...] |
| undefined.c | 126 cp15_trapper(u_int addr, u_int insn, struct trapframe *tf, int code)
140 const u_int regno = (insn >> 12) & 15;
152 if ((insn & 0xffff0fff) == 0xee1d0f70) {
162 if ((insn & 0xffef0fff) == 0xee0d0f50) {
164 if (insn & 0x00100000)
177 gdb_trapper(u_int addr, u_int insn, struct trapframe *tf, int code)
183 if (insn == GDB_THUMB_BREAKPOINT)
189 if (insn == GDB_BREAKPOINT || insn == GDB5_BREAKPOINT) {
221 vfp_test(u_int address, u_int insn, trapframe_t *frame, int fault_code
261 u_int insn = read_insn(addr, false); local in function:dtrace_trapper
[all...] |
| /src/sys/arch/powerpc/powerpc/ |
| fix_unaligned.c | 37 * - Fetch and decode insn; 403 does not have DSISR.
39 * - Only for integer insn; unaligned floating-point load/store are taken
40 * care of by FPU emulator. (Support for FPU insn should be trivial.)
133 #define DISASM(tf, insn) \
136 opc_disasm((tf)->tf_srr0, (insn)->i_int); \
139 #define DISASM(tf, insn) __nothing
152 union instr insn; local in function:fix_unaligned
157 ret = ufetch_32((uint32_t *)tf->tf_srr0, (uint32_t *)&insn.i_int);
169 if (emul_unaligned(tf, ksi, &insn))
172 CTASSERT(sizeof(insn) == 4); /* It was broken before... *
[all...] |
| process_machdep.c | 292 ppc_ifetch(struct lwp *l, vaddr_t va, uint32_t *insn)
297 iov.iov_base = insn;
298 iov.iov_len = sizeof(*insn);
302 uio.uio_resid = sizeof(*insn);
310 ppc_istore(struct lwp *l, vaddr_t va, uint32_t insn)
315 iov.iov_base = &insn;
316 iov.iov_len = sizeof(insn);
320 uio.uio_resid = sizeof(insn);
339 uint32_t insn; local in function:ppc_sstep
353 if ((rv = ppc_ifetch(l, va[0], &insn)) != 0
[all...] |
| fix_unaligned.c | 37 * - Fetch and decode insn; 403 does not have DSISR.
39 * - Only for integer insn; unaligned floating-point load/store are taken
40 * care of by FPU emulator. (Support for FPU insn should be trivial.)
133 #define DISASM(tf, insn) \
136 opc_disasm((tf)->tf_srr0, (insn)->i_int); \
139 #define DISASM(tf, insn) __nothing
152 union instr insn; local in function:fix_unaligned
157 ret = ufetch_32((uint32_t *)tf->tf_srr0, (uint32_t *)&insn.i_int);
169 if (emul_unaligned(tf, ksi, &insn))
172 CTASSERT(sizeof(insn) == 4); /* It was broken before... *
[all...] |
| process_machdep.c | 292 ppc_ifetch(struct lwp *l, vaddr_t va, uint32_t *insn)
297 iov.iov_base = insn;
298 iov.iov_len = sizeof(*insn);
302 uio.uio_resid = sizeof(*insn);
310 ppc_istore(struct lwp *l, vaddr_t va, uint32_t insn)
315 iov.iov_base = &insn;
316 iov.iov_len = sizeof(insn);
320 uio.uio_resid = sizeof(insn);
339 uint32_t insn; local in function:ppc_sstep
353 if ((rv = ppc_ifetch(l, va[0], &insn)) != 0
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/engine/gr/ |
| nouveau_nvkm_engine_gr_nv40.c | 118 u32 insn = nvkm_rd32(device, 0x400308); local in function:nv40_gr_chan_fini
119 nvkm_warn(subdev, "ctxprog timeout %08x\n", insn);
|
| nouveau_nvkm_engine_gr_nv40.c | 118 u32 insn = nvkm_rd32(device, 0x400308); local in function:nv40_gr_chan_fini
119 nvkm_warn(subdev, "ctxprog timeout %08x\n", insn);
|
| /src/sys/arch/sparc/sparc/ |
| trap.c | 173 "insn access MMU miss", /* 3c */
819 u_int insn; local in function:mem_access_fault
820 if (ufetch_int((void *)pc, &insn) == 0 &&
821 (insn & 0xc1680000) == 0xc0680000) {
|
| /src/libexec/ld.elf_so/arch/alpha/ |
| alpha_reloc.c | 409 uint32_t insn[3], *stubptr; local in function:_rtld_relocate_plt_object
460 * First, build an LDA insn to adjust the low 16
463 insn[insncnt++] = 0x08 << 26 | 27 << 21 | 27 << 16 |
476 insn[insncnt++] = 0x09 << 26 | 27 << 21 |
506 insn[insncnt++] = 0x09 << 26 | 27 << 21 |
512 insn[insncnt++] = 0x29 << 26 | 27 << 21 |
519 * Now, build a JMP or BR insn to jump to the target. If
521 * we can use the more efficient BR insn. Otherwise, we
527 insn[insncnt++] = 0x30 << 26 | 31 << 21 |
531 insn[insncnt++] = 0x1a << 26 | 31 << 21
[all...] |
