| /src/regress/sys/uvm/pdsim/ |
| pdsim.c | 48 int irr[MAXID]; variable in typeref:typename:int[]
89 printf("%d %d # FREE IRR\n", idx, irr[idx]);
188 irr[index] = ts - lastacc[index];
280 stats[i].hit, stats[i].fault, irr[i]);
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| pdsim.c | 48 int irr[MAXID]; variable in typeref:typename:int[]
89 printf("%d %d # FREE IRR\n", idx, irr[idx]);
188 irr[index] = ts - lastacc[index];
280 stats[i].hit, stats[i].fault, irr[i]);
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| /src/sys/arch/cesfic/cesfic/ |
| dp8570a.h | 9 u_int8_t irr; member in struct:dp8570reg::__anon23a44c9f010a::__anon23a44c9f0208
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| dp8570a.h | 9 u_int8_t irr; member in struct:dp8570reg::__anon23a44c9f010a::__anon23a44c9f0208
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| /src/sys/arch/algor/algor/ |
| algor_p4032_intr.c | 280 u_int32_t irr; local in function:algor_p4032_cal_timer
306 irr = REGVAL(P4032_IRR0);
308 } while ((irr & IRR0_RTC) == 0);
420 u_int32_t irr[NIRQREG]; local in function:algor_p4032_iointr
424 irr[IRQREG_ERROR] = REGVAL(p4032_irqregs[IRQREG_ERROR].addr);
425 if (irr[IRQREG_ERROR] & IRR1_BUSERR)
427 if (irr[IRQREG_ERROR] & IRR1_POWERFAIL)
429 if (irr[IRQREG_ERROR] & IRR1_DEBUG) {
442 REGVAL(p4032_irqregs[IRQREG_ERROR].addr) = irr[IRQREG_ERROR];
462 irr[i] = REGVAL(p4032_irqregs[i].addr) & p4032_irqregs[i].val
[all...] |
| algor_p4032_intr.c | 280 u_int32_t irr; local in function:algor_p4032_cal_timer
306 irr = REGVAL(P4032_IRR0);
308 } while ((irr & IRR0_RTC) == 0);
420 u_int32_t irr[NIRQREG]; local in function:algor_p4032_iointr
424 irr[IRQREG_ERROR] = REGVAL(p4032_irqregs[IRQREG_ERROR].addr);
425 if (irr[IRQREG_ERROR] & IRR1_BUSERR)
427 if (irr[IRQREG_ERROR] & IRR1_POWERFAIL)
429 if (irr[IRQREG_ERROR] & IRR1_DEBUG) {
442 REGVAL(p4032_irqregs[IRQREG_ERROR].addr) = irr[IRQREG_ERROR];
462 irr[i] = REGVAL(p4032_irqregs[i].addr) & p4032_irqregs[i].val
[all...] |
| algor_p5064_intr.c | 366 uint32_t irr; local in function:algor_p5064_cal_timer
392 irr = REGVAL(P5064_LOCINT);
394 } while ((irr & LOCINT_RTC) == 0);
513 uint32_t irr[NIRQREG]; local in function:algor_p5064_iointr
517 irr[IRQREG_PANIC] = REGVAL(p5064_irqregs[IRQREG_PANIC].addr);
518 if (irr[IRQREG_PANIC] & PANIC_IOPERR)
520 if (irr[IRQREG_PANIC] & PANIC_ISANMI)
522 if (irr[IRQREG_PANIC] & PANIC_BERR)
524 if (irr[IRQREG_PANIC] & PANIC_PFAIL)
526 if (irr[IRQREG_PANIC] & PANIC_DEBUG)
[all...] |
| algor_p5064_intr.c | 366 uint32_t irr; local in function:algor_p5064_cal_timer
392 irr = REGVAL(P5064_LOCINT);
394 } while ((irr & LOCINT_RTC) == 0);
513 uint32_t irr[NIRQREG]; local in function:algor_p5064_iointr
517 irr[IRQREG_PANIC] = REGVAL(p5064_irqregs[IRQREG_PANIC].addr);
518 if (irr[IRQREG_PANIC] & PANIC_IOPERR)
520 if (irr[IRQREG_PANIC] & PANIC_ISANMI)
522 if (irr[IRQREG_PANIC] & PANIC_BERR)
524 if (irr[IRQREG_PANIC] & PANIC_PFAIL)
526 if (irr[IRQREG_PANIC] & PANIC_DEBUG)
[all...] |
| /src/sys/dev/ic/ |
| we.c | 566 uint8_t hwr, gcr, irr; local in function:we_set_media
584 irr = bus_space_read_1(wsc->sc_asict, wsc->sc_asich, WE_IRR);
586 irr |= WE_IRR_OUT2;
588 irr &= ~WE_IRR_OUT2;
589 bus_space_write_1(wsc->sc_asict, wsc->sc_asich, WE_IRR, irr);
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| we.c | 566 uint8_t hwr, gcr, irr; local in function:we_set_media
584 irr = bus_space_read_1(wsc->sc_asict, wsc->sc_asich, WE_IRR);
586 irr |= WE_IRR_OUT2;
588 irr &= ~WE_IRR_OUT2;
589 bus_space_write_1(wsc->sc_asict, wsc->sc_asich, WE_IRR, irr);
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| /src/sys/arch/zaurus/zaurus/ |
| machdep.c | 577 uint16_t mcr, cdr, csr, cpr, ccr, irr, irm, imr, isr; local in function:hw_isc1000
585 irr = ioreg16_read(baseaddr + SCOOP_IRR);
594 irr == 0 && irm == 0 && imr == 0 && isr == 0 &&
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| machdep.c | 577 uint16_t mcr, cdr, csr, cpr, ccr, irr, irm, imr, isr; local in function:hw_isc1000
585 irr = ioreg16_read(baseaddr + SCOOP_IRR);
594 irr == 0 && irm == 0 && imr == 0 && isr == 0 &&
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| /src/sys/external/mit/xen-include-public/dist/xen/include/public/arch-x86/hvm/ |
| save.h | 311 uint8_t irr; member in struct:hvm_hw_vpic
329 /* Reads from A=0 obtain ISR or IRR? */
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| save.h | 311 uint8_t irr; member in struct:hvm_hw_vpic
329 /* Reads from A=0 obtain ISR or IRR? */
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