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    Searched defs:level (Results 1 - 25 of 189) sorted by relevancy

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  /src/sys/fs/v7fs/
v7fs_datablock.h 47 int level; /* direct, index1, index2, index3 */ member in struct:v7fs_daddr_map
  /src/usr.sbin/inetd/
ipsec.c 128 int level; local in function:ipsecsetup0
135 level = IPPROTO_IP;
140 level = IPPROTO_IPV6;
151 if (commit && setsockopt(fd, level, opt,
  /src/usr.bin/indent/
parse.c 59 int level = 0; local in function:left_justify_decl_level
62 level++;
63 return level;
  /src/include/
ftw.h 53 int level; member in struct:FTW
  /src/lib/libc/db/btree/
bt_search.c 158 int level; local in function:__bt_snext
180 for (level = 0; (parent = BT_POP(t)) != NULL; ++level) {
196 while (level--) {
197 /* Push the next level down onto the stack. */
205 /* Get the next level down. */
235 int level; local in function:__bt_sprev
258 for (level = 0; (parent = BT_POP(t)) != NULL; ++level) {
273 while (level--)
    [all...]
  /src/sys/dev/mvme/
clmpcc_pcctwo.c 115 int level = pa->pa_ipl; local in function:clmpcc_pcctwo_attach
119 level = pa->pa_ipl;
131 sc->sc_evcnt = pcctwointr_evcnt(level);
137 pcctwointr_establish(PCCTWOV_SCC_RX, clmpcc_rxintr, level, sc, NULL);
138 pcctwointr_establish(PCCTWOV_SCC_RX_EXCEP, clmpcc_rxintr, level, sc,
140 pcctwointr_establish(PCCTWOV_SCC_TX, clmpcc_txintr, level, sc, NULL);
141 pcctwointr_establish(PCCTWOV_SCC_MODEM, clmpcc_mdintr, level, sc, NULL);
  /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/core/
nouveau_nvkm_core_option.c 102 int mode = 1, level = CONFIG_NOUVEAU_DEBUG_DEFAULT; local in function:nvkm_dbgopt
115 level = NV_DBG_FATAL;
117 level = NV_DBG_ERROR;
119 level = NV_DBG_WARN;
121 level = NV_DBG_INFO;
123 level = NV_DBG_DEBUG;
125 level = NV_DBG_TRACE;
127 level = NV_DBG_PARANOIA;
129 level = NV_DBG_SPAM;
138 return level;
    [all...]
  /src/tests/lib/libc/sys/
t_ptrace.c 119 int level; local in function:ATF_TC_BODY
120 size_t len = sizeof(level);
122 RL(sysctlbyname("kern.securelevel", &level, &len, NULL, 0));
124 if (level < 0) {
  /src/sys/arch/evbmips/mipssim/
mipssim_intr.c 45 * given hardware interrupt priority level.
111 for (int level = NINTR - 1; level >= 0; level--) { local in function:evbmips_iointr
114 if ((ipending & (MIPS_INT_MASK_0 << level)) == 0)
117 ih_count[level].ev_count++;
118 list = &intrs[level];
  /src/usr.sbin/mtree/
verify.c 82 NODE *ep, *level; local in function:vwalk
91 level = root;
108 for (level = level->parent; level->prev;
109 level = level->prev)
126 for (ep = level; ep; ep = ep->next)
138 level = ep->child;
  /src/sys/arch/x86/x86/
identcpu_subr.c 219 int type, level, ways, partitions, linesize, sets, totalsize; local in function:cpu_dcp_cacheinfo
228 level = __SHIFTOUT(descs[0], CPUID_DCP_CACHELEVEL);
229 switch (level) {
x86_softintr.c 166 int irq, level; local in function:x86_intr_calculatemasks
185 /* Then figure out which IRQs use each level. */
186 for (level = 0; level < NIPL; level++) {
189 if (intrlevel[irq] & (1ULL << level))
191 ci->ci_imask[level] = irqs | unusedirqs;
194 for (level = 0; level<(NIPL-1); level++
    [all...]
  /src/sys/arch/arm/iomd/
iomd_irqhandler.c 134 int level; local in function:irq_claim
156 /* Make sure the level is valid */
207 level = ptr->ih_level - 1;
210 if (ptr->ih_level - 1 < level)
211 level = ptr->ih_level - 1;
217 while (max_level >=0 && max_level > level) {
221 while (level >= 0) {
222 irqmasks[level] |= (1 << irq);
223 --level;
252 int level; local in function:irq_release
    [all...]
  /src/sys/arch/arm/nvidia/
tegra_lic.c 146 const u_int level = (trig & FDT_INTR_TYPE_DOUBLE_EDGE) local in function:tegra_lic_establish
149 return intr_establish_xname(irq, ipl, level | iflags, func, arg,
  /src/sys/arch/arm/ofw/
ofw_irqhandler.c 112 int level; local in function:irq_claim
133 /* Make sure the level is valid */
173 level = ptr->ih_level - 1;
175 if (ptr->ih_level - 1 < level)
176 level = ptr->ih_level - 1;
179 while (level >= 0) {
180 irqmasks[level] |= (1 << irq);
181 --level;
209 int level; local in function:irq_release
255 for (level = 0; level < NIPL; ++level
    [all...]
  /src/sys/arch/arm/s3c2xx0/
s3c2xx0_intr.h 201 int level; member in struct:s3c2xx0_intr_dispatch
  /src/sys/arch/evbarm/g42xxeb/
g42xxeb_var.h 63 int level; member in struct:obio_softc::obio_handler
gb225var.h 67 int level; member in struct:opio_softc::opio_intr_handler
  /src/sys/arch/mips/adm5120/
adm5120_intr.c 88 * given hardware interrupt priority level.
270 for (int level = NINTRS - 1; level >= 0; level--) { local in function:evbmips_iointr
271 if ((ipending & (MIPS_INT_MASK_0 << level)) == 0)
274 if (level)
279 adm5120_cpuintrs[level].cintr_count.ev_count++;
280 LIST_FOREACH(ih, &adm5120_cpuintrs[level].cintr_list, ih_q) {
  /src/sys/arch/shark/isa/
isa_irqhandler.c 169 /* Make sure the level is valid */
273 int irq, level; local in function:irq_calculatemasks
285 /* Then figure out which IRQs use each level. */
286 for (level = 0; level < NIPL; level++) {
289 if (irqlevel[irq] & (1 << level))
291 irqmasks[level] = ~irqs;
310 intr_claim(int irq, int level, int (*ih_func)(void *), void *ih_arg, const char *group, const char *name)
315 ih->ih_level = level;
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  /src/sys/dev/acpi/
acpi_debug.c 69 const char *layer, *level; local in function:acpi_debug_init
107 CTLFLAG_READWRITE, CTLTYPE_STRING, "level",
108 SYSCTL_DESCR("ACPI debug level"),
125 level = acpi_debug_getkey(acpi_debug_level_d, AcpiDbgLevel);
128 strlcpy(acpi_debug_level_s, level, ACPI_DEBUG_MAX);
225 * The default debug level.
  /src/sys/dev/scsipi/
scsipi_ioctl.c 126 * The lower level routines that call us here, will free the xs and restart
298 * better try. If user-level type command, we must
378 int level = *((int *)addr); local in function:scsipi_do_ioctl
380 SC_DEBUG(periph, SCSIPI_DB3, ("debug set to %d\n", level));
382 if (level & 1)
384 if (level & 2)
386 if (level & 4)
388 if (level & 8)
  /src/sys/external/bsd/drm2/dist/drm/i915/gem/
i915_gem_domain.c 176 * Changes the cache-level of an object across all VMA.
178 * @cache_level: new cache level to set for the object
180 * After this function returns, the object will be in the new cache-level
182 * with respect to the new cache-level. In order to keep the backing storage
183 * coherent for all users, we only allow a single cache level to be set
217 /* The cache-level will be applied when each vma is rebound. */
262 enum i915_cache_level level; local in function:i915_gem_set_caching_ioctl
267 level = I915_CACHE_NONE;
279 level = I915_CACHE_LLC;
282 level = HAS_WT(i915) ? I915_CACHE_WT : I915_CACHE_NONE
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/i915/gt/uc/
intel_guc_log.h 31 * While we're using plain log level in i915, GuC controls are much more...
48 u32 level; member in struct:intel_guc_log
70 int intel_guc_log_set_level(struct intel_guc_log *log, u32 level);
81 return log->level;
  /src/usr.bin/ctags/
C.c 65 int level; /* brace level */ local in function:c_entries
68 int t_level; /* typedef's brace level */
73 sp = tok; token = t_def = NO; t_level = -1; level = 0; lineno = 1;
88 ++level;
92 * if level goes below zero, try and fix
95 if (--level < 0)
96 level = 0;
150 * level zero indicates a function.
159 if (!level && token)
266 int level = 0; \/* for matching '()' *\/ local in function:func_entry
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