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    Searched defs:link_width (Results 1 - 12 of 12) sorted by relevancy

  /src/sys/dev/pci/cxgb/
cxgb_adapter.h 322 uint32_t link_width; member in struct:adapter
cxgb_adapter.h 322 uint32_t link_width; member in struct:adapter
cxgb_adapter.h 322 uint32_t link_width; member in struct:adapter
  /src/sys/dev/pci/
if_bnxvar.h 156 uint16_t link_width; /* PCIe link width */ member in struct:bnx_softc
if_bnxvar.h 156 uint16_t link_width; /* PCIe link width */ member in struct:bnx_softc
if_bnxvar.h 156 uint16_t link_width; /* PCIe link width */ member in struct:bnx_softc
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
amdgpu_smu7_hwmgr.c 169 uint32_t link_width; local in function:smu7_get_current_pcie_lane_number
172 link_width = PHM_READ_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
175 PP_ASSERT_WITH_CODE((7 >= link_width),
178 return decode_pcie_lane_width(link_width);
amdgpu_smu7_hwmgr.c 169 uint32_t link_width; local in function:smu7_get_current_pcie_lane_number
172 link_width = PHM_READ_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
175 PP_ASSERT_WITH_CODE((7 >= link_width),
178 return decode_pcie_lane_width(link_width);
amdgpu_smu7_hwmgr.c 169 uint32_t link_width; local in function:smu7_get_current_pcie_lane_number
172 link_width = PHM_READ_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
175 PP_ASSERT_WITH_CODE((7 >= link_width),
178 return decode_pcie_lane_width(link_width);
  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_ci_dpm.c 4831 u32 link_width = 0; local in function:ci_get_current_pcie_lane_number
4833 link_width = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL) & LC_LINK_WIDTH_RD_MASK;
4834 link_width >>= LC_LINK_WIDTH_RD_SHIFT;
4836 switch (link_width) {
radeon_ci_dpm.c 4831 u32 link_width = 0; local in function:ci_get_current_pcie_lane_number
4833 link_width = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL) & LC_LINK_WIDTH_RD_MASK;
4834 link_width >>= LC_LINK_WIDTH_RD_SHIFT;
4836 switch (link_width) {
radeon_ci_dpm.c 4831 u32 link_width = 0; local in function:ci_get_current_pcie_lane_number
4833 link_width = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL) & LC_LINK_WIDTH_RD_MASK;
4834 link_width >>= LC_LINK_WIDTH_RD_SHIFT;
4836 switch (link_width) {

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