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Searched defs:ln0 (Results 1 - 8 of 8) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/i915/display/
intel_ddi.c	2533 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) 2534 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) 2535 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) 2659 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) 2660 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) 2661 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) 3181 u32 ln0, ln1, pin_assignment; local in function:icl_program_mg_dp_mode 3189 ln0 = I915_READ(DKL_DP_MODE(tc_port)); 3193 ln0 = I915_READ(MG_DP_MODE(0, tc_port)); 3197 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE \| MG_DP_MODE_CFG_DP_X1_MODE) [all...]
intel_ddi.c	2533 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) 2534 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) 2535 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) 2659 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) 2660 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) 2661 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) 3181 u32 ln0, ln1, pin_assignment; local in function:icl_program_mg_dp_mode 3189 ln0 = I915_READ(DKL_DP_MODE(tc_port)); 3193 ln0 = I915_READ(MG_DP_MODE(0, tc_port)); 3197 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE \| MG_DP_MODE_CFG_DP_X1_MODE) [all...]
intel_ddi.c	2533 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) 2534 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) 2535 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) 2659 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) 2660 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) 2661 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) 3181 u32 ln0, ln1, pin_assignment; local in function:icl_program_mg_dp_mode 3189 ln0 = I915_READ(DKL_DP_MODE(tc_port)); 3193 ln0 = I915_READ(MG_DP_MODE(0, tc_port)); 3197 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE \| MG_DP_MODE_CFG_DP_X1_MODE) [all...]
intel_ddi.c	2533 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) 2534 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) 2535 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) 2659 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) 2660 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) 2661 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) 3181 u32 ln0, ln1, pin_assignment; local in function:icl_program_mg_dp_mode 3189 ln0 = I915_READ(DKL_DP_MODE(tc_port)); 3193 ln0 = I915_READ(MG_DP_MODE(0, tc_port)); 3197 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE \| MG_DP_MODE_CFG_DP_X1_MODE) [all...]
intel_ddi.c	2533 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) 2534 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) 2535 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) 2659 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) 2660 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) 2661 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) 3181 u32 ln0, ln1, pin_assignment; local in function:icl_program_mg_dp_mode 3189 ln0 = I915_READ(DKL_DP_MODE(tc_port)); 3193 ln0 = I915_READ(MG_DP_MODE(0, tc_port)); 3197 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE \| MG_DP_MODE_CFG_DP_X1_MODE) [all...]
intel_ddi.c	2533 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) 2534 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) 2535 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) 2659 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) 2660 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) 2661 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) 3181 u32 ln0, ln1, pin_assignment; local in function:icl_program_mg_dp_mode 3189 ln0 = I915_READ(DKL_DP_MODE(tc_port)); 3193 ln0 = I915_READ(MG_DP_MODE(0, tc_port)); 3197 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE \| MG_DP_MODE_CFG_DP_X1_MODE) [all...]
intel_ddi.c	2533 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) 2534 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) 2535 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) 2659 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) 2660 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) 2661 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) 3181 u32 ln0, ln1, pin_assignment; local in function:icl_program_mg_dp_mode 3189 ln0 = I915_READ(DKL_DP_MODE(tc_port)); 3193 ln0 = I915_READ(MG_DP_MODE(0, tc_port)); 3197 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE \| MG_DP_MODE_CFG_DP_X1_MODE) [all...]
intel_ddi.c	2533 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) 2534 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) 2535 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) 2659 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) 2660 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) 2661 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) 3181 u32 ln0, ln1, pin_assignment; local in function:icl_program_mg_dp_mode 3189 ln0 = I915_READ(DKL_DP_MODE(tc_port)); 3193 ln0 = I915_READ(MG_DP_MODE(0, tc_port)); 3197 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE \| MG_DP_MODE_CFG_DP_X1_MODE) [all...]

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